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basic ARM semihosting support
[openocd.git] / NEWS
diff --git a/NEWS b/NEWS
index a0bf43c21ff0e120ed915bc5185b1dc37d1b56b1..38ae4da6211ff815fad7cc587a9984cb662a62f4 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -8,12 +8,28 @@ JTAG Layer:
 
 Boundary Scan:
 Target Layer:
+       General
+               - new "reset-assert" event, for systems without SRST
        ARM
                - renamed "armv4_5" command prefix as "arm"
+               - recognize TrustZone "Secure Monitor" mode
+               - "arm regs" command output changed
+               - register names use "sp" not "r13"
+               - add top-level "mcr" and "mrc" commands, replacing
+                 various core-specific operations
+               - basic semihosting support
        ARM11
                - Preliminary ETM and ETB hookup
                - accelerated "flash erase_check"
                - accelerated GDB memory checksum
+               - support "arm regs" command
+               - can access all core modes and registers
+       Cortex-A8
+               - support "arm regs" command
+               - can access all core modes and registers
+               - supports "reset-assert" event (used on OMAP3530)
+       Cortex-M3
+               - Exposed DWT registers like cycle counter
 
 Flash Layer:
        'flash bank' and 'nand device' take <bank_name> as first argument.
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