# script for stm32l if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME stm32l } if { [info exists ENDIAN] } { set _ENDIAN $ENDIAN } else { set _ENDIAN little } # Work-area is a space in RAM used for flash programming # By default use 10kB if { [info exists WORKAREASIZE] } { set _WORKAREASIZE $WORKAREASIZE } else { set _WORKAREASIZE 0x2800 } # JTAG speed should be <= F_CPU/6. # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz adapter_khz 100 adapter_nsrst_delay 100 jtag_ntrst_delay 100 #jtag scan chain if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { # See STM Document RM0038 # Section 24.6.3 set _CPUTAPID 0x4ba00477 } jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID if { [info exists BSTAPID] } { # FIXME this never gets used to override defaults... set _BSTAPID $BSTAPID } else { # See STM Document RM0038 # Section 24.6.2 set _BSTAPID 0x06416041 } jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 # flash size will be probed set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME # if srst is not fitted use SYSRESETREQ to # perform a soft reset cortex_m reset_config sysresetreq proc stm32l_enable_HSI {} { # Enable HSI as clock source echo "STM32L: Enabling HSI" # Set HSION in RCC_CR mww 0x40023800 0x00000101 # Set HSI as SYSCLK mww 0x40023808 0x00000001 # Increase JTAG speed adapter_khz 2000 } $_TARGETNAME configure -event reset-init { stm32l_enable_HSI }