# script for stm32h7x family # # stm32h7 devices support both JTAG and SWD transports. # source [find target/swj-dp.tcl] source [find mem_helper.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME stm32h7x } set _ENDIAN little # Work-area is a space in RAM used for flash programming # By default use 64kB if { [info exists WORKAREASIZE] } { set _WORKAREASIZE $WORKAREASIZE } else { set _WORKAREASIZE 0x10000 } #jtag scan chain if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { if { [using_jtag] } { set _CPUTAPID 0x6ba00477 } { set _CPUTAPID 0x6ba02477 } } swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu if {[using_jtag]} { swj_newdap $_CHIPNAME bs -irlen 5 } if {![using_hla]} { # STM32H7 provides an APB-AP at access port 2, which allows the access to # the debug and trace features on the system APB System Debug Bus (APB-D). target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 } set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME # Clock after reset is HSI at 64 MHz, no need of PLL adapter_khz 1800 adapter_nsrst_delay 100 if {[using_jtag]} { jtag_ntrst_delay 100 } # use hardware reset # # The STM32H7 does not support connect_assert_srst mode because the AXI is # unavailable while SRST is asserted, and that is used to access the DBGMCU # component at 0x5C001000 in the examine-end event handler. # # It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead # of the default AP0, and that works with SRST asserted; however, nonzero AP # usage does not work with HLA, so is not done by default. That change could be # made in a local configuration file if connect_assert_srst mode is needed for # a specific application and a non-HLA adapter is in use. reset_config srst_only srst_nogate if {![using_hla]} { # if srst is not fitted use SYSRESETREQ to # perform a soft reset cortex_m reset_config sysresetreq # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 # makes the data access cacheable. This allows reading and writing data in the # CPU cache from the debugger, which is far more useful than going straight to # RAM when operating on typical variables, and is generally no worse when # operating on special memory locations. $_CHIPNAME.dap apcsw 0x08000000 0x08000000 } $_TARGETNAME configure -event examine-end { # Enable D3 and D1 DBG clocks # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN stm32h7x_dbgmcu_mmw 0x004 0x00600000 0 # Enable debug during low power modes (uses more power) # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains stm32h7x_dbgmcu_mmw 0x004 0x00000187 0 # Stop watchdog counters during halt # DBGMCU_APB3FZ1 |= WWDG1 stm32h7x_dbgmcu_mmw 0x034 0x00000040 0 # DBGMCU_APB4FZ1 |= WDGLSD1 stm32h7x_dbgmcu_mmw 0x054 0x00040000 0 } $_TARGETNAME configure -event trace-config { # Set TRACECLKEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment stm32h7x_dbgmcu_mmw 0x004 0x00100000 0 } $_TARGETNAME configure -event reset-init { # Clock after reset is HSI at 64 MHz, no need of PLL adapter_khz 4000 } # like mrw, but with target selection proc stm32h7x_mrw {used_target reg} { set value "" $used_target mem2array value 32 $reg 1 return $value(0) } # like mmw, but with target selection proc stm32h7x_mmw {used_target reg setbits clearbits} { set old [stm32h7x_mrw $used_target $reg] set new [expr ($old & ~$clearbits) | $setbits] $used_target mww $reg $new } # mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base # this procedure will use the mem_ap on AP2 whenever possible proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} { # use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address if {![using_hla]} { # get _CHIPNAME from the current target set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""] set used_target $_CHIPNAME.ap2 set reg_addr [expr 0xE00E1000 + $reg_offset] } { set used_target [target current] set reg_addr [expr 0x5C001000 + $reg_offset] } stm32h7x_mmw $used_target $reg_addr $setbits $clearbits }