# SPDX-License-Identifier: GPL-2.0-or-later

# NXP QN908x Cortex-M4F with 128 KiB SRAM

source [find target/swj-dp.tcl]

set CHIPNAME qn908x
set CHIPSERIES qn9080
if { ![info exists WORKAREASIZE] } {
  set WORKAREASIZE 0x20000
}

# SWD IDCODE (Cortex M4).
set CPUTAPID 0x2ba01477

swj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID
dap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu

set TARGETNAME $CHIPNAME.cpu
target create $TARGETNAME cortex_m -dap $CHIPNAME.dap

# SRAM is mapped at 0x04000000.
$TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE

# flash bank <name> qn908x <base> <size> 0 0 <target#> [calc_checksum]
# The base must be set as 0x01000000, and the size parameter is unused.
set FLASHNAME $CHIPNAME.flash
flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum

# We write directly to flash memory over this adapter interface. For debugging
# this could in theory be faster (the Core clock on reset is normally at 32MHz),
# but for flashing 1MHz is more reliable.
adapter speed 1000

# Delay on reset line.
adapter srst delay 200

cortex_m reset_config sysresetreq