# OMAP4430 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME omap4430 } # Although the OMAP4430 supposedly has an ICEpick-D, only the # ICEpick-C router commands seem to work. # See http://processors.wiki.ti.com/index.php/ICEPICK source [find target/icepick.cfg] # # A9 DAP # if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID } else { set _DAP_TAPID 0x3BA00477 } jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_DAP_TAPID -disable jtag configure $_CHIPNAME.cpu -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 9" # # M3 DAPs, one per core # if { [info exists M3_DAP_TAPID] } { set _M3_DAP_TAPID $M3_DAP_TAPID } else { set _M3_DAP_TAPID 0x4BA00477 } jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M3_DAP_TAPID -disable jtag configure $_CHIPNAME.m31 -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 5" jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M3_DAP_TAPID -disable jtag configure $_CHIPNAME.m30 -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 4" # # ICEpick-D JRC (JTAG route controller) # if { [info exists JRC_TAPID] } { set _JRC_TAPID $JRC_TAPID } else { set _JRC_TAPID 0x3b95c02f set _JRC_TAPID2 0x1b85202f } # PandaBoard REV EA1 (PEAP platforms) if { [info exists JRC_TAPID2] } { set _JRC_TAPID2 $JRC_TAPID2 } else { set _JRC_TAPID2 0x1b85202f } jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2 # Required by ICEpick to power-up the debug domain jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200" # # GDB target: Cortex-A9, using DAP # # The debugger can connect to either core of the A9, but currently # not both simultaneously. Change -coreid to 1 to connect to the # second core. # set _TARGETNAME $_CHIPNAME.cpu # APB DBGBASE reads 0x80040000, but this points to an empty ROM table. # 0x80000000 is cpu0 coresight region # # # CORTEX_A8_PADDRDBG_CPU_SHIFT 13 # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) set _coreid 0 set _dbgbase [expr 0x80000000 | ($_coreid << 13)] echo "Using dbgbase = [format 0x%x $_dbgbase]" dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \ -coreid 0 -dbgbase $_dbgbase # SRAM: 56KiB at 0x4030.0000 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 # # M3 targets, separate TAP/DAP for each core # dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30 dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31 target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap # Once the JRC is up, enable our TAPs jtag configure $_CHIPNAME.jrc -event setup " jtag tapenable $_CHIPNAME.cpu jtag tapenable $_CHIPNAME.m30 jtag tapenable $_CHIPNAME.m31 " # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset # ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset. set PRM_RSTCTRL 0x4A307B00 $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1" $_CHIPNAME.m30 configure -event reset-assert { } $_CHIPNAME.m31 configure -event reset-assert { } # Soft breakpoints don't currently work due to broken cache handling gdb_breakpoint_override hard