source [find target/swj-dp.tcl] adapter_khz 500 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME lpc4350 } # # M4 JTAG mode TAP # if { [info exists M4_JTAG_TAPID] } { set _M4_JTAG_TAPID $M4_JTAG_TAPID } else { set _M4_JTAG_TAPID 0x4ba00477 } # # M4 SWD mode TAP # if { [info exists M4_SWD_TAPID] } { set _M4_SWD_TAPID $M4_SWD_TAPID } else { set _M4_SWD_TAPID 0x2ba01477 } if { [using_jtag] } { set _M4_TAPID $_M4_JTAG_TAPID } { set _M4_TAPID $_M4_SWD_TAPID } # # M0 TAP # if { [info exists M0_JTAG_TAPID] } { set _M0_JTAG_TAPID $M0_JTAG_TAPID } else { set _M0_JTAG_TAPID 0x0ba01477 } swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M4_TAPID target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 if { [using_jtag] } { swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M0_JTAG_TAPID target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0 } # LPC4350 has 96+32 KB SRAM if { [info exists WORKAREASIZE] } { set _WORKAREASIZE $WORKAREASIZE } else { set _WORKAREASIZE 0x20000 } $_CHIPNAME.m4 configure -work-area-phys 0x10000000 \ -work-area-size $_WORKAREASIZE -work-area-backup 0 if {![using_hla]} { # on this CPU we should use VECTRESET to perform a soft reset and # manually reset the periphery # SRST or SYSRESETREQ disable the debug interface for the time of # the reset and will not fit our requirements for a consistent debug # session cortex_m reset_config vectreset }