# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM, set CHIPNAME lpc1788 set CPUTAPID 0x4ba00477 set CPURAMSIZE 0x10000 set CPUROMSIZE 0x80000 # After reset the chip is clocked by the ~12MHz internal RC oscillator. # When board-specific code (reset-init handler or device firmware) # configures another oscillator and/or PLL0, set CCLK to match; if # you don't, then flash erase and write operations may misbehave. # (The ROM code doing those updates cares about core clock speed...) # # CCLK is the core clock frequency in KHz set CCLK 12000 #Include the main configuration file. source [find target/lpc17xx.cfg]; # if srst is not fitted, use SYSRESETREQ to perform a soft reset cortex_m reset_config sysresetreq