testing/examples/LPC2294Test/src/crt.s

   1 /****************************************************************************
   2 *  Copyright (c) 2006 by Michael Fischer. All rights reserved.
   3 *
   4 *  Redistribution and use in source and binary forms, with or without
   5 *  modification, are permitted provided that the following conditions
   6 *  are met:
   7 *
   8 *  1. Redistributions of source code must retain the above copyright
   9 *     notice, this list of conditions and the following disclaimer.
  10 *  2. Redistributions in binary form must reproduce the above copyright
  11 *     notice, this list of conditions and the following disclaimer in the
  12 *     documentation and/or other materials provided with the distribution.
  13 *  3. Neither the name of the author nor the names of its contributors may
  14 *     be used to endorse or promote products derived from this software
  15 *     without specific prior written permission.
  16 *
  17 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20 *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21 *  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25 *  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26 *  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27 *  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28 *  SUCH DAMAGE.
  29 *
  30 ****************************************************************************
  31 *
  32 *  History:
  33 *
  34 *  31.03.06  mifi   First Version
  35 *                   This version based on an example from Ethernut and
  36 *                   "ARM Cross Development with Eclipse" from James P. Lynch
  37 ****************************************************************************/
  38
  39 /*
  40  * Some defines for the program status registers
  41  */
  42    ARM_MODE_USER  = 0x10      /* Normal User Mode                             */
  43    ARM_MODE_FIQ   = 0x11      /* FIQ Fast Interrupts Mode                     */
  44    ARM_MODE_IRQ   = 0x12      /* IRQ Standard Interrupts Mode                 */
  45    ARM_MODE_SVC   = 0x13      /* Supervisor Interrupts Mode                   */
  46    ARM_MODE_ABORT = 0x17      /* Abort Processing memory Faults Mode          */
  47    ARM_MODE_UNDEF = 0x1B      /* Undefined Instructions Mode                  */
  48    ARM_MODE_SYS   = 0x1F      /* System Running in Priviledged Operating Mode */
  49    ARM_MODE_MASK  = 0x1F
  50
  51    I_BIT          = 0x80      /* disable IRQ when I bit is set */
  52    F_BIT          = 0x40      /* disable IRQ when I bit is set */
  53
  54 /*
  55  * Register Base Address
  56  */
  57
  58    .section .vectors,"ax"
  59    .code 32
  60
  61 /****************************************************************************/
  62 /*               Vector table and reset entry                               */
  63 /****************************************************************************/
  64 _vectors:
  65    ldr pc, ResetAddr    /* Reset                 */
  66    ldr pc, UndefAddr    /* Undefined instruction */
  67    ldr pc, SWIAddr      /* Software interrupt    */
  68    ldr pc, PAbortAddr   /* Prefetch abort        */
  69    ldr pc, DAbortAddr   /* Data abort            */
  70    ldr pc, ReservedAddr /* Reserved              */
  71    ldr pc, IRQAddr      /* IRQ interrupt         */
  72    ldr pc, FIQAddr      /* FIQ interrupt         */
  73
  74
  75 ResetAddr:     .word ResetHandler
  76 UndefAddr:     .word UndefHandler
  77 SWIAddr:       .word SWIHandler
  78 PAbortAddr:    .word PAbortHandler
  79 DAbortAddr:    .word DAbortHandler
  80 ReservedAddr:  .word 0
  81 IRQAddr:       .word IRQHandler
  82 FIQAddr:       .word FIQHandler
  83
  84    .ltorg
  85
  86
  87    .section .init, "ax"
  88    .code 32
  89
  90    .global ResetHandler
  91    .global ExitFunction
  92    .extern main
  93 /****************************************************************************/
  94 /*                           Reset handler                                  */
  95 /****************************************************************************/
  96 ResetHandler:
  97 /*
  98  * Wait for the oscillator is stable
  99  */
 100    nop
 101    nop
 102    nop
 103    nop
 104    nop
 105    nop
 106    nop
 107    nop
 108
 109    /*
 110     * Setup a stack for each mode
 111     */
 112    msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */
 113    ldr   sp, =__stack_und_end
 114
 115    msr   CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT   /* Abort Mode */
 116    ldr   sp, =__stack_abt_end
 117
 118    msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */
 119    ldr   sp, =__stack_fiq_end
 120
 121    msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */
 122    ldr   sp, =__stack_irq_end
 123
 124    msr   CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT     /* Supervisor Mode */
 125    ldr   sp, =__stack_svc_end
 126
 127
 128    /*
 129     * Clear .bss section
 130     */
 131    ldr   r1, =__bss_start
 132    ldr   r2, =__bss_end
 133    ldr   r3, =0
 134 bss_clear_loop:
 135    cmp   r1, r2
 136    strne r3, [r1], #+4
 137    bne   bss_clear_loop
 138
 139
 140    /*
 141     * Jump to main
 142     */
 143    mrs   r0, cpsr
 144    bic   r0, r0, #I_BIT | F_BIT     /* Enable FIQ and IRQ interrupt */
 145    msr   cpsr, r0
 146
 147    mov   r0, #0 /* No arguments */
 148    mov   r1, #0 /* No arguments */
 149    ldr   r2, =main
 150    mov   lr, pc
 151    bx    r2     /* And jump... */
 152
 153 ExitFunction:
 154    nop
 155    nop
 156    nop
 157    b ExitFunction
 158
 159
 160 /****************************************************************************/
 161 /*                         Default interrupt handler                        */
 162 /****************************************************************************/
 163
 164 UndefHandler:
 165    b UndefHandler
 166
 167 SWIHandler:
 168    b SWIHandler
 169
 170 PAbortHandler:
 171    b PAbortHandler
 172
 173 DAbortHandler:
 174    b DAbortHandler
 175
 176 IRQHandler:
 177    b IRQHandler
 178
 179 FIQHandler:
 180    b FIQHandler
 181
 182    .weak ExitFunction
 183    .weak UndefHandler, PAbortHandler, DAbortHandler
 184    .weak IRQHandler, FIQHandler
 185
 186    .ltorg
 187 /*** EOF ***/
 188
 189