testing/examples/AT91R40008Test/src/crt.s

   1 /****************************************************************************
   2 *  Copyright (c) 2006 by Michael Fischer. All rights reserved.
   3 *
   4 *  Redistribution and use in source and binary forms, with or without
   5 *  modification, are permitted provided that the following conditions
   6 *  are met:
   7 *
   8 *  1. Redistributions of source code must retain the above copyright
   9 *     notice, this list of conditions and the following disclaimer.
  10 *  2. Redistributions in binary form must reproduce the above copyright
  11 *     notice, this list of conditions and the following disclaimer in the
  12 *     documentation and/or other materials provided with the distribution.
  13 *  3. Neither the name of the author nor the names of its contributors may
  14 *     be used to endorse or promote products derived from this software
  15 *     without specific prior written permission.
  16 *
  17 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  20 *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21 *  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  22 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25 *  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26 *  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  27 *  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28 *  SUCH DAMAGE.
  29 *
  30 ****************************************************************************
  31 *
  32 *  History:
  33 *
  34 *  09.04.06  mifi   First Version
  35 ****************************************************************************/
  36
  37 /*
  38  * Some defines for the program status registers
  39  */
  40    ARM_MODE_USER  = 0x10      /* Normal User Mode                             */
  41    ARM_MODE_FIQ   = 0x11      /* FIQ Fast Interrupts Mode                     */
  42    ARM_MODE_IRQ   = 0x12      /* IRQ Standard Interrupts Mode                 */
  43    ARM_MODE_SVC   = 0x13      /* Supervisor Interrupts Mode                   */
  44    ARM_MODE_ABORT = 0x17      /* Abort Processing memory Faults Mode          */
  45    ARM_MODE_UNDEF = 0x1B      /* Undefined Instructions Mode                  */
  46    ARM_MODE_SYS   = 0x1F      /* System Running in Priviledged Operating Mode */
  47    ARM_MODE_MASK  = 0x1F
  48
  49    I_BIT          = 0x80      /* disable IRQ when I bit is set */
  50    F_BIT          = 0x40      /* disable IRQ when I bit is set */
  51
  52
  53    .section .vectors,"ax"
  54    .code 32
  55
  56 /****************************************************************************/
  57 /*               Vector table and reset entry                               */
  58 /****************************************************************************/
  59 _vectors:
  60    ldr pc, ResetAddr    /* Reset                 */
  61    ldr pc, UndefAddr    /* Undefined instruction */
  62    ldr pc, SWIAddr      /* Software interrupt    */
  63    ldr pc, PAbortAddr   /* Prefetch abort        */
  64    ldr pc, DAbortAddr   /* Data abort            */
  65    ldr pc, ReservedAddr /* Reserved              */
  66    ldr pc, IRQAddr      /* IRQ interrupt         */
  67    ldr pc, FIQAddr      /* FIQ interrupt         */
  68
  69
  70 ResetAddr:     .word ResetHandler
  71 UndefAddr:     .word UndefHandler
  72 SWIAddr:       .word SWIHandler
  73 PAbortAddr:    .word PAbortHandler
  74 DAbortAddr:    .word DAbortHandler
  75 ReservedAddr:  .word 0
  76 IRQAddr:       .word IRQHandler
  77 FIQAddr:       .word FIQHandler
  78
  79    .ltorg
  80
  81
  82    .section .init, "ax"
  83    .code 32
  84
  85    .global ResetHandler
  86    .global ExitFunction
  87    .extern main
  88 /****************************************************************************/
  89 /*                           Reset handler                                  */
  90 /****************************************************************************/
  91 ResetHandler:
  92    /*
  93     * Setup a stack for each mode
  94     */
  95    msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */
  96    ldr   sp, =__stack_und_end
  97
  98    msr   CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT   /* Abort Mode */
  99    ldr   sp, =__stack_abt_end
 100
 101    msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */
 102    ldr   sp, =__stack_fiq_end
 103
 104    msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */
 105    ldr   sp, =__stack_irq_end
 106
 107    msr   CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT     /* Supervisor Mode */
 108    ldr   sp, =__stack_svc_end
 109
 110
 111    /*
 112     * Clear .bss section
 113     */
 114    ldr   r1, =__bss_start
 115    ldr   r2, =__bss_end
 116    ldr   r3, =0
 117 bss_clear_loop:
 118    cmp   r1, r2
 119    strne r3, [r1], #+4
 120    bne   bss_clear_loop
 121
 122
 123    /*
 124     * Jump to main
 125     */
 126    mrs   r0, cpsr
 127    bic   r0, r0, #I_BIT | F_BIT     /* Enable FIQ and IRQ interrupt */
 128    msr   cpsr, r0
 129
 130    mov   r0, #0 /* No arguments */
 131    mov   r1, #0 /* No arguments */
 132    ldr   r2, =main
 133    mov   lr, pc
 134    bx    r2     /* And jump... */
 135
 136 ExitFunction:
 137    nop
 138    nop
 139    nop
 140    b ExitFunction
 141
 142
 143 /****************************************************************************/
 144 /*                         Default interrupt handler                        */
 145 /****************************************************************************/
 146
 147 UndefHandler:
 148    b UndefHandler
 149
 150 SWIHandler:
 151    b SWIHandler
 152
 153 PAbortHandler:
 154    b PAbortHandler
 155
 156 DAbortHandler:
 157    b DAbortHandler
 158
 159 IRQHandler:
 160    b IRQHandler
 161
 162 FIQHandler:
 163    b FIQHandler
 164
 165    .weak ExitFunction
 166    .weak UndefHandler, PAbortHandler, DAbortHandler
 167    .weak IRQHandler, FIQHandler
 168
 169    .ltorg
 170 /*** EOF ***/
 171
 172