tcl/target/zynq_7000.cfg

   1 #
   2 # Xilinx Zynq-7000 All Programmable SoC
   3 #
   4 # http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
   5 #
   6
   7 set _CHIPNAME zynq
   8 set _TARGETNAME $_CHIPNAME.cpu
   9
  10 jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
  11     -expected-id 0x23727093 \
  12     -expected-id 0x13722093 \
  13     -expected-id 0x03727093 \
  14     -expected-id 0x03736093
  15
  16 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
  17
  18 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  19
  20 target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
  21     -coreid 0 -dbgbase 0x80090000
  22 target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
  23     -coreid 1 -dbgbase 0x80092000
  24 target smp ${_TARGETNAME}0 ${_TARGETNAME}1
  25
  26 adapter_khz 1000
  27
  28 ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
  29 ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
  30
  31 pld device virtex2 zynq_pl.bs 1
  32
  33 set XC7_JSHUTDOWN 0x0d
  34 set XC7_JPROGRAM 0x0b
  35 set XC7_JSTART 0x0c
  36 set XC7_BYPASS 0x3f
  37
  38 proc zynqpl_program {tap} {
  39         global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
  40         irscan $tap $XC7_JSHUTDOWN
  41         irscan $tap $XC7_JPROGRAM
  42         runtest 60000
  43         #JSTART prevents this from working...
  44         #irscan $tap $XC7_JSTART
  45         runtest 2000
  46         irscan $tap $XC7_BYPASS
  47         runtest 2000
  48 }