u8500.cfg : ste u8500 support
[openocd.git] / tcl / target / u8500.cfg
1 # Copyright (C) ST-Ericsson SA 2011
2 # Author : michel.jaouen@stericsson.com
3 # U8500 target
4
5 proc mmu_off {} {
6 set cp [arm mrc 15 0 1 0 0]
7 set cp [expr ($cp & ~1)]
8 arm mcr 15 0 1 0 0 $cp
9 }
10
11 proc mmu_on {} {
12 set cp [arm mrc 15 0 1 0 0]
13 set cp [expr ($cp | 1)]
14 arm mcr 15 0 1 0 0 $cp
15 }
16
17 proc ocd_gdb_restart {target_id} {
18 global _TARGETNAME_1
19 global _SMP
20 targets $_TARGETNAME_1
21 if { [expr ($_SMP == 1)] } {
22 cortex_a8 smp_off
23 }
24 rst_run
25 halt
26 if { [expr ($_SMP == 1)]} {
27 cortex_a8 smp_on
28 }
29 }
30
31 proc smp_reg {} {
32 global _TARGETNAME_1
33 global _TARGETNAME_2
34 targets $_TARGETNAME_1
35 echo "$_TARGETNAME_1"
36 set pc1 [reg pc]
37 set stck1 [reg sp_svc]
38 targets $_TARGETNAME_2
39 echo "$_TARGETNAME_1"
40 set pc2 [reg pc]
41 set stck2 [reg sp_svc]
42 }
43
44
45 proc u8500_tapenable {chip val} {
46 echo "JTAG tap enable $chip"
47 }
48
49
50 proc pwrsts { } {
51 global _CHIPNAME
52 irscan $_CHIPNAME.jrc 0x3a
53 drscan $_CHIPNAME.jrc 4 0
54 set pwrsts [drscan $_CHIPNAME.jrc 16 0]
55 echo "pwrsts ="$pwrsts
56 set a9 [expr (0x$pwrsts & 0xc)]
57 set ape [expr (0x$pwrsts & 0x3)]
58 if {[string equal "0" $ape]} {
59 echo "ape off"
60 } else {
61 echo "ape on"
62 }
63 echo "$a9"
64 switch $a9 {
65 4 {
66 echo "A9 in retention"
67 }
68 8 {
69 echo "A9 100% DVFS"
70 }
71 c {
72 echo "A9 50% DVFS"
73 }
74 }
75 }
76
77 proc poll_pwrsts { } {
78 global _CHIPNAME
79 set result 1
80 set i 0
81 irscan $_CHIPNAME.jrc 0x3a
82 drscan $_CHIPNAME.jrc 4 0
83 set pwrsts [drscan $_CHIPNAME.jrc 16 0]
84 set pwrsts [expr (0x$pwrsts & 0xc)]
85 while {[string equal "4" $pwrsts] && $i<20} {
86 irscan $_CHIPNAME.jrc 0x3a
87 drscan $_CHIPNAME.jrc 4 0;
88 set pwrsts [drscan $_CHIPNAME.jrc 16 0]
89 set pwrsts [expr (0x$pwrsts & 0xc)]
90 if {![string equal "4" $pwrsts]} {
91 set result 1
92 } else {
93 set result 0
94 sleep 200
95 echo "loop $i"
96 }
97 incr i
98 }
99 return $result
100 }
101
102 proc halt_ { } {
103 if {[poll_pwrsts]==1} {
104 halt
105 } else {
106 echo "halt failed : target in retention"
107 }
108 }
109
110
111 proc u8500_dapenable {chip} {
112 }
113
114 proc u8500_tapdisable {chip val} {
115 echo "JTAG tap disable $chip"
116 }
117
118
119 proc enable_apetap {} {
120 global _CHIPNAME
121 global _TARGETNAME_2
122 global _TARGETNAME_1
123 poll off
124 irscan $_CHIPNAME.jrc 0x3e
125 drscan $_CHIPNAME.jrc 8 0xcf
126 jtag tapenable $_CHIPNAME.dap
127 irscan $_CHIPNAME.jrc 0x6
128 drscan $_CHIPNAME.jrc 32 0
129 irscan $_CHIPNAME.jrc 0x6
130 drscan $_CHIPNAME.jrc 32 0
131 set status [$_TARGETNAME_1 curstate]
132 if {[string equal "unknown" $status]} {
133 $_TARGETNAME_1 arp_examine
134 }
135 set status [$_TARGETNAME_2 curstate]
136 if {[string equal "unknown" $status]} {
137 $_TARGETNAME_2 arp_examine
138 }
139 }
140
141 tcl_port 5555
142 telnet_port 4444
143 gdb_port 3333
144
145 if { [info exists CHIPNAME] } {
146 global _CHIPNAME
147 set _CHIPNAME $CHIPNAME
148 } else {
149 global _CHIPNAME
150 set _CHIPNAME u8500
151 }
152
153 if { [info exists ENDIAN] } {
154 set _ENDIAN $ENDIAN
155 } else {
156 # this defaults to a bigendian
157 set _ENDIAN little
158 }
159
160
161
162 # Subsidiary TAP: APE with scan chains for ARM Debug, EmbeddedICE-RT,
163 if { [info exists CPUTAPID ] } {
164 set _CPUTAPID $CPUTAPID
165 } else {
166 set _CPUTAPID 0x4ba00477
167 }
168 jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable
169 jtag configure $_CHIPNAME.dap -event tap-enable \
170 "u8500_dapenable $_CHIPNAME.dap"
171 jtag configure $_CHIPNAME.dap -event tap-disable \
172 "u8500_tapdisable $_CHIPNAME.dap 0xc0"
173
174
175 #CLTAPC TAP JRC equivalent
176 if { [info exists CLTAPC_ID ] } {
177 set _CLTAPC_ID $CLTAPC_ID
178 } else {
179 set _CLTAPC_ID 0x22286041
180 }
181 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x6 -irmask 0xf -expected-id $_CLTAPC_ID -ignore-version
182
183
184 if { ![info exists TARGETNAME_1 ] } {
185 global _TARGETNAME_1
186 set _TARGETNAME_1 $_CHIPNAME.cpu1
187 } else {
188 global _TARGETNAME_1
189 set _TARGETNAME_1 $TARGETNAME_1
190 }
191
192 if { [info exists DAP_DBG1] } {
193 set _DAP_DBG1 $DAP_DBG1
194 } else {
195 set _DAP_DBG1 0x801A8000
196 }
197 if { [info exists DAP_DBG2] } {
198 set _DAP_DBG2 $DAP_DBG2
199 } else {
200 set _DAP_DBG2 0x801AA000
201 }
202
203 target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0
204
205 $_TARGETNAME_1 configure -event gdb-attach {
206 halt
207 }
208
209
210 if { ![info exists TARGETNAME_2 ] } {
211 global _TARGETNAME_2
212 set _TARGETNAME_2 $_CHIPNAME.cpu2
213 } else {
214 global _TARGETNAME_2
215 set _TARGETNAME_2 $TARGETNAME_2
216 }
217
218 target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1
219
220 $_TARGETNAME_2 configure -event gdb-attach {
221 halt
222 }
223
224
225 if {![info exists SMP]} {
226 global _SMP
227 set _SMP 1
228 } else {
229 global _SMP
230 set _SMP $SMP
231 }
232 global SMP
233 if { $_SMP == 1} {
234 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
235 }
236
237 proc secsts1 { } {
238 global _CHIPNAME
239 irscan $_CHIPNAME.jrc 0x3a
240 drscan $_CHIPNAME.jrc 4 4
241 set secsts1 [drscan $_CHIPNAME.jrc 16 0]
242 echo "secsts1 ="$secsts1
243 set secsts1 [expr (0x$secsts1 & 0x4)]
244 if {![string equal "4" $secsts1]} {
245 echo "APE target secured"
246 } else {
247 echo "APE target not secured"
248 }
249 }
250
251 proc att { } {
252 global _CHIPNAME
253 jtag arp_init
254 irscan $_CHIPNAME.jrc 0x3a
255 drscan $_CHIPNAME.jrc 4 4
256 set secsts1 [drscan $_CHIPNAME.jrc 16 0]
257 echo "secsts1 ="$secsts1
258 set secsts1 [expr (0x$secsts1 & 0x4)]
259 if {[string equal "4" $secsts1]} {
260 if {[poll_pwrsts]==1} {
261 enable_apetap
262 } else {
263 echo "target in retention"
264 }
265 } else {
266 echo "target secured"
267 }
268 }
269
270
271
272 proc rst_run { } {
273 global _CHIPNAME
274 global _TARGETNAME_2
275 global _TARGETNAME_1
276 set status [$_TARGETNAME_1 curstate]
277 if {[string equal "halted" $status]} {
278 resume
279 targets $_TARGETNAME_1
280 }
281 set status [$_TARGETNAME_2 curstate]
282 if {[string equal "halted" $status]} {
283 resume
284 targets $_TARGETNAME_2
285 }
286 poll off
287 jtag arp_init
288 reset
289 sleep 20
290 irscan $_CHIPNAME.jrc 0x3a
291 drscan $_CHIPNAME.jrc 4 4
292 set secsts1 [drscan $_CHIPNAME.jrc 16 0]
293 echo "secsts1 ="$secsts1
294 set secsts1 [expr (0x$secsts1 & 0x4)]
295 while {![string equal "4" $secsts1]} {
296 irscan u8500.jrc 0x3a
297 drscan u8500.jrc 4 4
298 set secsts1 [drscan $_CHIPNAME.jrc 16 0]
299 echo "secsts1 ="$secsts1
300 set secsts1 [expr (0x$secsts1 & 0x4)]
301 }
302 echo "ape debugable"
303 enable_apetap
304 poll on
305 targets $_TARGETNAME_1
306 dap apsel 1
307 }
308
309 if {![info exists MAXSPEED]} {
310 global _MAXSPEED
311 set _MAXSPEED 15000
312 } else {
313 global _MAXSPEED
314 set _MAXSPEED $MAXSPEED
315 }
316 global _MAXSPEED
317 adapter_khz $_MAXSPEED
318
319
320 gdb_breakpoint_override hard
321 set mem inaccessible-by-default-off
322
323 jtag_ntrst_delay 100
324 reset_config trst_and_srst combined
325
326

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