tcl/target/ti_dm355.cfg

   1 #
   2 # Texas Instruments DaVinci family:  TMS320DM355
   3 #
   4 if { [info exists CHIPNAME] } {
   5    set  _CHIPNAME $CHIPNAME
   6 } else {
   7    set  _CHIPNAME dm355
   8 }
   9 if { [info exists ENDIAN] } {
  10    set  _ENDIAN $ENDIAN
  11 } else {
  12    set  _ENDIAN little
  13 }
  14
  15 #
  16 # For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
  17 # are enabled without making ICEpick route ARM and ETB into the JTAG chain.
  18 #
  19 # Also note:  when running without RTCK before the PLLs are set up, you
  20 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
  21 #
  22
  23 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  24 if { [info exists ETB_TAPID ] } {
  25    set _ETB_TAPID $ETB_TAPID
  26 } else {
  27    set _ETB_TAPID 0x2b900f0f
  28 }
  29 jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
  30
  31 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  32 if { [info exists CPU_TAPID ] } {
  33    set _CPU_TAPID $CPU_TAPID
  34 } else {
  35    set _CPU_TAPID 0x07926001
  36 }
  37 jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
  38
  39 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
  40 if { [info exists JRC_TAPID ] } {
  41    set _JRC_TAPID $JRC_TAPID
  42 } else {
  43    set _JRC_TAPID 0x0b73b02f
  44 }
  45 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
  46
  47 ################
  48
  49 # various symbol definitions, to avoid hard-wiring addresses
  50 # and enable some sharing of DaVinci-family utility code
  51 global dm355
  52 set dm355 [ dict create ]
  53
  54 # Physical addresses for controllers and memory
  55 # (Some of these are valid for many DaVinci family chips)
  56 dict set dm355 sram0            0x00010000
  57 dict set dm355 sram1            0x00014000
  58 dict set dm355 sysbase          0x01c40000
  59 dict set dm355 pllc1            0x01c40800
  60 dict set dm355 pllc2            0x01c40c00
  61 dict set dm355 psc              0x01c41000
  62 dict set dm355 gpio             0x01c67000
  63 dict set dm355 a_emif           0x01e10000
  64 dict set dm355 a_emif_cs0       0x02000000
  65 dict set dm355 a_emif_cs1       0x04000000
  66 dict set dm355 ddr_emif         0x20000000
  67 dict set dm355 ddr              0x80000000
  68 dict set dm355 uart0            0x01c20000
  69 dict set dm355 uart1            0x01c20400
  70 dict set dm355 uart2            0x01e06000
  71
  72 source [find target/davinci.cfg]
  73
  74 ################
  75 # GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
  76 # and the ETB memory (4K) are other options, while trace is unused.
  77 set _TARGETNAME $_CHIPNAME.arm
  78
  79 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
  80
  81 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
  82 # and that the work area is used only with a kernel mmu context ...
  83 $_TARGETNAME configure \
  84         -work-area-virt [expr 0xfffe0000 + 0x4000] \
  85         -work-area-phys [dict get $dm355 sram1] \
  86         -work-area-size 0x4000 \
  87         -work-area-backup 0
  88
  89 # be absolutely certain the JTAG clock will work with the worst-case
  90 # CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
  91 # on the PLL and starts using it.  OK to speed up after clock setup.
  92 jtag_rclk 1500
  93 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
  94
  95 arm7_9 fast_memory_access enable
  96 arm7_9 dcc_downloads enable
  97
  98 # trace setup
  99 etm config $_TARGETNAME 16 normal full etb
 100 etb config $_TARGETNAME $_CHIPNAME.etb