tcl/target/ti_dm355.cfg

   1 #
   2 # Texas Instruments DaVinci family: TMS320DM355
   3 #
   4 if { [info exists CHIPNAME] } {
   5    set _CHIPNAME $CHIPNAME
   6 } else {
   7    set _CHIPNAME dm355
   8 }
   9
  10 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
  11 # after JTAG reset until ICEpick is used to route them in.
  12 set EMU01 "-disable"
  13
  14 # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
  15 # needing any ICEpick interaction.
  16 #set EMU01 "-enable"
  17
  18 source [find target/icepick.cfg]
  19
  20 #
  21 # Also note: when running without RTCK before the PLLs are set up, you
  22 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
  23 #
  24
  25 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  26 if { [info exists ETB_TAPID] } {
  27    set _ETB_TAPID $ETB_TAPID
  28 } else {
  29    set _ETB_TAPID 0x2b900f0f
  30 }
  31 jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
  32 jtag configure $_CHIPNAME.etb -event tap-enable \
  33         "icepick_c_tapenable $_CHIPNAME.jrc 1"
  34
  35 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  36 if { [info exists CPU_TAPID] } {
  37    set _CPU_TAPID $CPU_TAPID
  38 } else {
  39    set _CPU_TAPID 0x07926001
  40 }
  41 jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
  42 jtag configure $_CHIPNAME.arm -event tap-enable \
  43         "icepick_c_tapenable $_CHIPNAME.jrc 0"
  44
  45 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
  46 if { [info exists JRC_TAPID] } {
  47    set _JRC_TAPID $JRC_TAPID
  48 } else {
  49    set _JRC_TAPID 0x0b73b02f
  50 }
  51 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
  52
  53 jtag configure $_CHIPNAME.jrc -event setup \
  54         "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
  55
  56 ################
  57
  58 # various symbol definitions, to avoid hard-wiring addresses
  59 # and enable some sharing of DaVinci-family utility code
  60 global dm355
  61 set dm355 [ dict create ]
  62
  63 # Physical addresses for controllers and memory
  64 # (Some of these are valid for many DaVinci family chips)
  65 dict set dm355 sram0            0x00010000
  66 dict set dm355 sram1            0x00014000
  67 dict set dm355 sysbase          0x01c40000
  68 dict set dm355 pllc1            0x01c40800
  69 dict set dm355 pllc2            0x01c40c00
  70 dict set dm355 psc              0x01c41000
  71 dict set dm355 gpio             0x01c67000
  72 dict set dm355 a_emif           0x01e10000
  73 dict set dm355 a_emif_cs0       0x02000000
  74 dict set dm355 a_emif_cs1       0x04000000
  75 dict set dm355 ddr_emif         0x20000000
  76 dict set dm355 ddr              0x80000000
  77 dict set dm355 uart0            0x01c20000
  78 dict set dm355 uart1            0x01c20400
  79 dict set dm355 uart2            0x01e06000
  80
  81 source [find target/davinci.cfg]
  82
  83 ################
  84 # GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
  85 # and the ETB memory (4K) are other options, while trace is unused.
  86 set _TARGETNAME $_CHIPNAME.arm
  87
  88 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  89
  90 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
  91 # and that the work area is used only with a kernel mmu context ...
  92 $_TARGETNAME configure \
  93         -work-area-virt [expr 0xfffe0000 + 0x4000] \
  94         -work-area-phys [dict get $dm355 sram1] \
  95         -work-area-size 0x4000 \
  96         -work-area-backup 0
  97
  98 # be absolutely certain the JTAG clock will work with the worst-case
  99 # CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
 100 # on the PLL and starts using it.  OK to speed up after clock setup.
 101 adapter_khz 1500
 102 $_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
 103
 104 arm7_9 fast_memory_access enable
 105 arm7_9 dcc_downloads enable
 106
 107 # trace setup
 108 etm config $_TARGETNAME 16 normal full etb
 109 etb config $_TARGETNAME $_CHIPNAME.etb