tcl/target/stm32wbx.cfg

   1 # script for stm32wbx family
   2
   3 #
   4 # stm32wb devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32wbx
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 64kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x10000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30       set _CPUTAPID 0x6ba00477
  31    } else {
  32       # SWD IDCODE (single drop, arm)
  33       set _CPUTAPID 0x6ba02477
  34    }
  35 }
  36
  37 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  38 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  39
  40 if {[using_jtag]} {
  41    jtag newtap $_CHIPNAME bs -irlen 5
  42 }
  43
  44 set _TARGETNAME $_CHIPNAME.cpu
  45 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  46
  47 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  48
  49 set _FLASHNAME $_CHIPNAME.flash
  50 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
  51
  52 # Common knowledges tells JTAG speed should be <= F_CPU/6.
  53 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
  54 # the safe side.
  55 #
  56 # Note that there is a pretty wide band where things are
  57 # more or less stable, see http://openocd.zylin.com/#/c/3366/
  58 adapter speed 500
  59
  60 adapter srst delay 100
  61 if {[using_jtag]} {
  62  jtag_ntrst_delay 100
  63 }
  64
  65 reset_config srst_nogate
  66
  67 if {![using_hla]} {
  68    # if srst is not fitted use SYSRESETREQ to
  69    # perform a soft reset
  70    cortex_m reset_config sysresetreq
  71 }
  72
  73 $_TARGETNAME configure -event reset-init {
  74     # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
  75     # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
  76     # 2 WS compliant with VOS=Range1 and 24 MHz.
  77     mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTBE | 2(Latency)
  78     mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
  79     # Boost JTAG frequency
  80     adapter speed 4000
  81 }
  82
  83 $_TARGETNAME configure -event reset-start {
  84     # Reset clock is MSI (4 MHz)
  85     adapter speed 500
  86 }
  87
  88 $_TARGETNAME configure -event examine-end {
  89     # Enable debug during low power modes (uses more power)
  90     # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  91     mmw 0xE0042004 0x00000007 0
  92
  93     # Stop watchdog counters during halt
  94     # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
  95     mmw 0xE004203C 0x00001800 0
  96 }
  97
  98 $_TARGETNAME configure -event trace-config {
  99     # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 100     # change this value accordingly to configure trace pins
 101     # assignment
 102     mmw 0xE0042004 0x00000020 0
 103 }