tcl/target/stm32l5x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32l5x family
   4
   5 #
   6 # stm32l5 devices support both JTAG and SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12         set _CHIPNAME $CHIPNAME
  13 } else {
  14         set _CHIPNAME stm32l5x
  15 }
  16
  17 set _ENDIAN little
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 64kB
  21 if { [info exists WORKAREASIZE] } {
  22         set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24         set _WORKAREASIZE 0x10000
  25 }
  26
  27 #jtag scan chain
  28 if { [info exists CPUTAPID] } {
  29         set _CPUTAPID $CPUTAPID
  30 } else {
  31         if { [using_jtag] } {
  32                 # See STM Document RM0438
  33                 # RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
  34                 # Corresponds to Cortex®-M33 JTAG debug port ID code
  35                 set _CPUTAPID 0x0ba04477
  36         } {
  37                 # SWD IDCODE (single drop, arm)
  38                 set _CPUTAPID 0x0be12477
  39         }
  40 }
  41
  42 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  43 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  44
  45 if {[using_jtag]} {
  46         jtag newtap $_CHIPNAME bs -irlen 5
  47 }
  48
  49 set _TARGETNAME $_CHIPNAME.cpu
  50 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  51
  52 # use non-secure RAM by default
  53 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  54
  55 # declare non-secure flash
  56 flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
  57 flash bank $_CHIPNAME.otp      stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
  58
  59 # Common knowledges tells JTAG speed should be <= F_CPU/6.
  60 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
  61 # the safe side.
  62 #
  63 # Note that there is a pretty wide band where things are
  64 # more or less stable, see http://openocd.zylin.com/#/c/3366/
  65 adapter speed 500
  66
  67 adapter srst delay 100
  68 if {[using_jtag]} {
  69         jtag_ntrst_delay 100
  70 }
  71
  72 reset_config srst_nogate
  73
  74 if {![using_hla]} {
  75         # if srst is not fitted use SYSRESETREQ to
  76         # perform a soft reset
  77         cortex_m reset_config sysresetreq
  78 }
  79
  80 proc clock_config_110_mhz {} {
  81         # MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
  82         # RCC_APB1ENR1 = PWREN
  83         mww 0x40021058 0x10000000
  84         # delay for register clock enable (read back reg)
  85         mrw 0x40021058
  86         # PWR_CR1 : VOS Range 0
  87         mww 0x40007000 0
  88         # while (PWR_SR2 & VOSF)
  89         while {([mrw 0x40007014] & 0x0400)} {}
  90         # FLASH_ACR : 5 WS for 110 MHz HCLK
  91         mww 0x40022000 0x00000005
  92         # RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
  93         # fVCO = 4 x 55 /1 = 220
  94         # SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
  95         mww 0x4002100C 0x01003711
  96         # RCC_CR |= PLLON
  97         mmw 0x40021000 0x01000000 0
  98         # while !(RCC_CR & PLLRDY)
  99         while {!([mrw 0x40021000] & 0x02000000)} {}
 100         # RCC_CFGR |= SW_PLL
 101         mmw 0x40021008 0x00000003 0
 102         # while ((RCC_CFGR & SWS) != PLL)
 103         while {([mrw 0x40021008] & 0x0C) != 0x0C} {}
 104 }
 105
 106 $_TARGETNAME configure -event reset-init {
 107         clock_config_110_mhz
 108         # Boost JTAG frequency
 109         adapter speed 4000
 110 }
 111
 112 $_TARGETNAME configure -event reset-start {
 113         # Reset clock is MSI (4 MHz)
 114         adapter speed 480
 115 }
 116
 117 $_TARGETNAME configure -event examine-end {
 118         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
 119         mmw 0xE0044004 0x00000006 0
 120
 121         # Stop watchdog counters during halt
 122         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
 123         mmw 0xE0044008 0x00001800 0
 124 }
 125
 126 $_TARGETNAME configure -event trace-config {
 127         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 128         # change this value accordingly to configure trace pins
 129         # assignment
 130         mmw 0xE0044004 0x00000020 0
 131 }