tcl/target/stm32l4x.cfg

   1 # script for stm32l4x family
   2
   3 #
   4 # stm32l4 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32l4x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # Smallest current target has 64kB ram, use 32kB by default to avoid surprises
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x8000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30       # See STM Document RM0351
  31       # Section 44.6.3 - corresponds to Cortex-M4 r0p1
  32       set _CPUTAPID 0x4ba00477
  33    } {
  34       set _CPUTAPID 0x2ba01477
  35    }
  36 }
  37
  38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  39
  40 if {[using_jtag]} {
  41    jtag newtap $_CHIPNAME bs -irlen 5
  42 }
  43
  44 set _TARGETNAME $_CHIPNAME.cpu
  45 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  46
  47 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  48
  49 set _FLASHNAME $_CHIPNAME.flash
  50 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
  51
  52 # Common knowledges tells JTAG speed should be <= F_CPU/6.
  53 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
  54 # the safe side.
  55 #
  56 # Note that there is a pretty wide band where things are
  57 # more or less stable, see http://openocd.zylin.com/#/c/3366/
  58 adapter_khz 500
  59
  60 adapter_nsrst_delay 100
  61 if {[using_jtag]} {
  62  jtag_ntrst_delay 100
  63 }
  64
  65 reset_config srst_nogate
  66
  67 if {![using_hla]} {
  68    # if srst is not fitted use SYSRESETREQ to
  69    # perform a soft reset
  70    cortex_m reset_config sysresetreq
  71 }
  72
  73 $_TARGETNAME configure -event reset-init {
  74         # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
  75         # Use MSI 24 MHz clock, compliant even with VOS == 2.
  76         # 3 WS compliant with VOS == 2 and 24 MHz.
  77         mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
  78         mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10
  79         # Boost JTAG frequency
  80         adapter_khz 4000
  81 }
  82
  83 $_TARGETNAME configure -event reset-start {
  84         # Reset clock is MSI (4 MHz)
  85         adapter_khz 500
  86 }
  87
  88 $_TARGETNAME configure -event examine-end {
  89         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  90         mmw 0xE0042004 0x00000007 0
  91
  92         # Stop watchdog counters during halt
  93         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  94         mmw 0xE0042008 0x00001800 0
  95 }
  96
  97 $_TARGETNAME configure -event trace-config {
  98         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  99         # change this value accordingly to configure trace pins
 100         # assignment
 101         mmw 0xE0042004 0x00000020 0
 102 }