tcl/target/stm32l1.cfg

   1 #
   2 # stm32l1 devices support both JTAG and SWD transports.
   3 #
   4
   5 source [find target/swj-dp.tcl]
   6 source [find mem_helper.tcl]
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME stm32l1
  12 }
  13
  14 set _ENDIAN little
  15
  16 # Work-area is a space in RAM used for flash programming
  17 # By default use 10kB
  18 if { [info exists WORKAREASIZE] } {
  19    set _WORKAREASIZE $WORKAREASIZE
  20 } else {
  21    set _WORKAREASIZE 0x2800
  22 }
  23
  24 # JTAG speed should be <= F_CPU/6.
  25 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
  26 adapter_khz 300
  27
  28 adapter_nsrst_delay 100
  29 if {[using_jtag]} {
  30  jtag_ntrst_delay 100
  31 }
  32
  33 #jtag scan chain
  34 if { [info exists CPUTAPID] } {
  35    set _CPUTAPID $CPUTAPID
  36 } else {
  37    if { [using_jtag] } {
  38       # See STM Document RM0038
  39       # Section 30.6.3 - corresponds to Cortex-M3 r2p0
  40       set _CPUTAPID 0x4ba00477
  41    } else {
  42       # SWD IDCODE (single drop, arm)
  43       set _CPUTAPID 0x2ba01477
  44    }
  45 }
  46
  47 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  48
  49 if { [info exists BSTAPID] } {
  50    # FIXME this never gets used to override defaults...
  51    set _BSTAPID $BSTAPID
  52 } else {
  53    # See STM Document RM0038 Section 30.6.1 Rev. 12
  54
  55    # Low and medium density
  56    set _BSTAPID1 0x06416041
  57    # Cat.2 device (medium+ density)
  58    set _BSTAPID2 0x06429041
  59    # Cat.3 device (medium+ density)
  60    set _BSTAPID3 0x06427041
  61    # Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
  62    set _BSTAPID4 0x06436041
  63    # Cat.5 device (high density), STM32L15/6xxE
  64    set _BSTAPID5 0x06437041
  65 }
  66
  67 if {[using_jtag]} {
  68    swj_newdap $_CHIPNAME bs -irlen 5 \
  69    -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
  70    -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
  71 }
  72
  73 set _TARGETNAME $_CHIPNAME.cpu
  74 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  75
  76 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  77
  78 # flash size will be probed
  79 set _FLASHNAME $_CHIPNAME.flash
  80 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  81
  82 reset_config srst_nogate
  83
  84 if {![using_hla]} {
  85    # if srst is not fitted use SYSRESETREQ to
  86    # perform a soft reset
  87    cortex_m reset_config sysresetreq
  88 }
  89
  90 proc stm32l_enable_HSI {} {
  91         # Enable HSI as clock source
  92         echo "STM32L: Enabling HSI"
  93
  94         # Set HSION in RCC_CR
  95         mww 0x40023800 0x00000101
  96
  97         # Set HSI as SYSCLK
  98         mww 0x40023808 0x00000001
  99
 100         # Increase JTAG speed
 101         adapter_khz 2000
 102 }
 103
 104 $_TARGETNAME configure -event reset-init {
 105         stm32l_enable_HSI
 106 }
 107
 108 $_TARGETNAME configure -event reset-start {
 109         adapter_khz 300
 110 }
 111
 112 $_TARGETNAME configure -event examine-end {
 113         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
 114         mmw 0xE0042004 0x00000007 0
 115
 116         # Stop watchdog counters during halt
 117         # DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
 118         mww 0xE0042008 0x00001800
 119 }
 120
 121 $_TARGETNAME configure -event trace-config {
 122         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 123         # change this value accordingly to configure trace pins
 124         # assignment
 125         mmw 0xE0042004 0x00000020 0
 126 }