tcl/target/stm32l0.cfg

   1 #
   2 # M0+ devices only have SW-DP, but swj-dp code works, just don't
   3 # set any jtag related features
   4 #
   5
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32l0
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 2kB (max ram on smallest part)
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x800
  23 }
  24
  25 # JTAG speed should be <= F_CPU/6.
  26 # F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
  27 adapter_khz 300
  28
  29 adapter_nsrst_delay 100
  30
  31 if { [info exists CPUTAPID] } {
  32     set _CPUTAPID $CPUTAPID
  33 } else {
  34     # Arm, m0+, non-multidrop.
  35     # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
  36     set _CPUTAPID 0x0bc11477
  37 }
  38
  39 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
  40 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  41
  42 set _TARGETNAME $_CHIPNAME.cpu
  43 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  44
  45 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  46
  47 # flash size will be probed
  48 set _FLASHNAME $_CHIPNAME.flash
  49 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
  50
  51 reset_config srst_nogate
  52
  53 if {![using_hla]} {
  54    # if srst is not fitted use SYSRESETREQ to
  55    # perform a soft reset
  56    cortex_m reset_config sysresetreq
  57 }
  58
  59 proc stm32l0_enable_HSI16 {} {
  60         # Enable HSI16 as clock source
  61         echo "STM32L0: Enabling HSI16"
  62
  63         # Set HSI16ON in RCC_CR (leave MSI enabled)
  64         mww 0x40021000 0x00000101
  65
  66         # Set HSI16 as SYSCLK (RCC_CFGR)
  67         mww 0x4002100c 0x00000001
  68
  69         # Increase speed
  70         adapter_khz 2500
  71 }
  72
  73 $_TARGETNAME configure -event reset-init {
  74         stm32l0_enable_HSI16
  75 }
  76
  77 $_TARGETNAME configure -event reset-start {
  78         adapter_khz 300
  79 }
  80
  81 $_TARGETNAME configure -event examine-end {
  82         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  83         mmw 0x40015804 0x00000007 0
  84
  85         # Stop watchdog counters during halt
  86         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  87         mmw 0x40015808 0x00001800 0
  88 }