tcl/target/stm32h7x.cfg

   1 # script for stm32h7x family
   2
   3 #
   4 # stm32h7 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32h7x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 64kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x10000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30           set _CPUTAPID 0x6ba00477
  31    } {
  32       set _CPUTAPID 0x6ba02477
  33    }
  34 }
  35
  36 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  37 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  38
  39 if {[using_jtag]} {
  40  swj_newdap $_CHIPNAME bs -irlen 5
  41 }
  42
  43 if {![using_hla]} {
  44         # STM32H7 provides an APB-AP at access port 2, which allows the access to
  45         # the debug and trace features on the system APB System Debug Bus (APB-D).
  46         target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
  47 }
  48
  49 set _TARGETNAME $_CHIPNAME.cpu
  50 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
  51
  52 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  53
  54 set _FLASHNAME $_CHIPNAME.flash
  55 flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
  56
  57 # Clock after reset is HSI at 64 MHz, no need of PLL
  58 adapter_khz 1800
  59
  60 adapter_nsrst_delay 100
  61 if {[using_jtag]} {
  62  jtag_ntrst_delay 100
  63 }
  64
  65 # use hardware reset
  66 #
  67 # The STM32H7 does not support connect_assert_srst mode because the AXI is
  68 # unavailable while SRST is asserted, and that is used to access the DBGMCU
  69 # component at 0x5C001000 in the examine-end event handler.
  70 #
  71 # It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
  72 # of the default AP0, and that works with SRST asserted; however, nonzero AP
  73 # usage does not work with HLA, so is not done by default. That change could be
  74 # made in a local configuration file if connect_assert_srst mode is needed for
  75 # a specific application and a non-HLA adapter is in use.
  76 reset_config srst_only srst_nogate
  77
  78 if {![using_hla]} {
  79    # if srst is not fitted use SYSRESETREQ to
  80    # perform a soft reset
  81    cortex_m reset_config sysresetreq
  82
  83    # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
  84    # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
  85    # makes the data access cacheable. This allows reading and writing data in the
  86    # CPU cache from the debugger, which is far more useful than going straight to
  87    # RAM when operating on typical variables, and is generally no worse when
  88    # operating on special memory locations.
  89    $_CHIPNAME.dap apcsw 0x08000000 0x08000000
  90 }
  91
  92 $_TARGETNAME configure -event examine-end {
  93         # Enable D3 and D1 DBG clocks
  94         # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
  95         stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
  96
  97         # Enable debug during low power modes (uses more power)
  98         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
  99         stm32h7x_dbgmcu_mmw 0x004 0x00000187 0
 100
 101         # Stop watchdog counters during halt
 102         # DBGMCU_APB3FZ1 |= WWDG1
 103         stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
 104         # DBGMCU_APB4FZ1 |= WDGLSD1
 105         stm32h7x_dbgmcu_mmw 0x054 0x00040000 0
 106 }
 107
 108 $_TARGETNAME configure -event trace-config {
 109         # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
 110         # change this value accordingly to configure trace pins
 111         # assignment
 112         stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
 113 }
 114
 115 $_TARGETNAME configure -event reset-init {
 116         # Clock after reset is HSI at 64 MHz, no need of PLL
 117         adapter_khz 4000
 118 }
 119
 120 # like mrw, but with target selection
 121 proc stm32h7x_mrw {used_target reg} {
 122         set value ""
 123         $used_target mem2array value 32 $reg 1
 124         return $value(0)
 125 }
 126
 127 # like mmw, but with target selection
 128 proc stm32h7x_mmw {used_target reg setbits clearbits} {
 129         set old [stm32h7x_mrw $used_target $reg]
 130         set new [expr ($old & ~$clearbits) | $setbits]
 131         $used_target mww $reg $new
 132 }
 133
 134 # mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
 135 # this procedure will use the mem_ap on AP2 whenever possible
 136 proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
 137         # use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
 138         if {![using_hla]} {
 139                 # get _CHIPNAME from the current target
 140                 set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""]
 141                 set used_target $_CHIPNAME.ap2
 142                 set reg_addr [expr 0xE00E1000 + $reg_offset]
 143         } {
 144                 set used_target [target current]
 145                 set reg_addr [expr 0x5C001000 + $reg_offset]
 146         }
 147
 148         stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
 149 }