tcl/target/stm32h7x.cfg

   1 # script for stm32h7x family
   2
   3 #
   4 # stm32h7 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32h7x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 64kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x10000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30           set _CPUTAPID 0x6ba00477
  31    } {
  32       set _CPUTAPID 0x6ba02477
  33    }
  34 }
  35
  36 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  37 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  38
  39 if {[using_jtag]} {
  40  swj_newdap $_CHIPNAME bs -irlen 5
  41 }
  42
  43 set _TARGETNAME $_CHIPNAME.cpu
  44 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  45
  46 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  47
  48 set _FLASHNAME $_CHIPNAME.flash
  49 flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
  50
  51 # Clock after reset is HSI at 64 MHz, no need of PLL
  52 adapter_khz 1800
  53
  54 adapter_nsrst_delay 100
  55 if {[using_jtag]} {
  56  jtag_ntrst_delay 100
  57 }
  58
  59 # use hardware reset, connect under reset
  60 reset_config srst_only srst_nogate
  61
  62 if {![using_hla]} {
  63    # if srst is not fitted use SYSRESETREQ to
  64    # perform a soft reset
  65    cortex_m reset_config sysresetreq
  66
  67    # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
  68    # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
  69    # makes the data access cacheable. This allows reading and writing data in the
  70    # CPU cache from the debugger, which is far more useful than going straight to
  71    # RAM when operating on typical variables, and is generally no worse when
  72    # operating on special memory locations.
  73    $_CHIPNAME.dap apcsw 0x08000000 0x08000000
  74 }
  75
  76 $_TARGETNAME configure -event examine-end {
  77         # Enable D3 and D1 DBG clocks
  78         # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
  79         mmw 0x5C001004 0x00600000 0
  80
  81         # Enable debug during low power modes (uses more power)
  82         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
  83         mmw 0x5C001004 0x00000187 0
  84
  85         # Stop watchdog counters during halt
  86         # DBGMCU_APB3FZ1 |= WWDG1
  87         mmw 0x5C001034 0x00000040 0
  88         # DBGMCU_APB4FZ1 |= WDGLSD1
  89         mmw 0x5C001054 0x00040000 0
  90 }
  91
  92 $_TARGETNAME configure -event trace-config {
  93         # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
  94         # change this value accordingly to configure trace pins
  95         # assignment
  96         mmw 0x5C001004 0x00100000 0
  97 }
  98
  99 $_TARGETNAME configure -event reset-init {
 100         # Clock after reset is HSI at 64 MHz, no need of PLL
 101         adapter_khz 4000
 102 }
 103