tcl/target/stm32g4x.cfg

   1 # script for stm32g4x family
   2
   3 #
   4 # stm32g4 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10         set _CHIPNAME $CHIPNAME
  11 } else {
  12         set _CHIPNAME stm32g4x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # Smallest current target has 32kB ram, use 16kB by default to avoid surprises
  19 if { [info exists WORKAREASIZE] } {
  20         set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22         set _WORKAREASIZE 0x4000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27         set _CPUTAPID $CPUTAPID
  28 } else {
  29         if { [using_jtag] } {
  30                 # See STM Document RM0440
  31                 # Section 46.6.3 - corresponds to Cortex-M4 r0p1
  32                 set _CPUTAPID 0x4ba00477
  33         } {
  34                 set _CPUTAPID 0x2ba01477
  35         }
  36 }
  37
  38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  39 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  40
  41 if {[using_jtag]} {
  42         jtag newtap $_CHIPNAME bs -irlen 5
  43 }
  44
  45 set _TARGETNAME $_CHIPNAME.cpu
  46 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  47
  48 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  49
  50 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
  51 flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
  52
  53 if { [info exists QUADSPI] && $QUADSPI } {
  54         set a [llength [flash list]]
  55         set _QSPINAME $_CHIPNAME.qspi
  56         flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
  57 }
  58
  59 # reasonable default
  60 adapter speed 2000
  61
  62 adapter srst delay 100
  63 if {[using_jtag]} {
  64         jtag_ntrst_delay 100
  65 }
  66
  67 reset_config srst_nogate
  68
  69 if {![using_hla]} {
  70         # if srst is not fitted use SYSRESETREQ to
  71         # perform a soft reset
  72         cortex_m reset_config sysresetreq
  73 }
  74
  75 $_TARGETNAME configure -event reset-init {
  76         # CPU comes out of reset with HSION | HSIRDY.
  77         # Use HSI 16 MHz clock, compliant even with VOS == 2.
  78         # 1 WS compliant with VOS == 2 and 16 MHz.
  79         mmw 0x40022000 0x00000001 0x0000000E    ;# FLASH_ACR: Latency = 1
  80         mmw 0x40021000 0x00000100 0x00000000    ;# RCC_CR |= HSION
  81         mmw 0x40021008 0x00000001 0x00000002    ;# RCC_CFGR: SW=HSI16
  82 }
  83
  84 $_TARGETNAME configure -event reset-start {
  85         # Reset clock is HSI (16 MHz)
  86         adapter speed 2000
  87 }
  88
  89 $_TARGETNAME configure -event examine-end {
  90         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  91         mmw 0xE0042004 0x00000007 0
  92
  93         # Stop watchdog counters during halt
  94         # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
  95         mmw 0xE0042008 0x00001800 0
  96 }
  97
  98 $_TARGETNAME configure -event trace-config {
  99         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 100         # change this value accordingly to configure trace pins
 101         # assignment
 102         mmw 0xE0042004 0x00000020 0
 103 }