tcl/target/stm32g0x.cfg

   1 # script for stm32g0x family
   2
   3 #
   4 # stm32g0 devices support SWD transports only.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10         set _CHIPNAME $CHIPNAME
  11 } else {
  12         set _CHIPNAME stm32g0x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
  19 if { [info exists WORKAREASIZE] } {
  20         set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22         set _WORKAREASIZE 0x1000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27         set _CPUTAPID $CPUTAPID
  28 } else {
  29         # Section 37.5.5 - corresponds to Cortex-M0+
  30         set _CPUTAPID 0x0bc11477
  31 }
  32
  33 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  34 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  35
  36 set _TARGETNAME $_CHIPNAME.cpu
  37 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  38
  39 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  40
  41 set _FLASHNAME $_CHIPNAME.flash
  42 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
  43
  44 # reasonable default
  45 adapter speed 2000
  46
  47 adapter srst delay 100
  48 if {[using_jtag]} {
  49         jtag_ntrst_delay 100
  50 }
  51
  52 reset_config srst_nogate
  53
  54 if {![using_hla]} {
  55         # if srst is not fitted use SYSRESETREQ to
  56         # perform a soft reset
  57         cortex_m reset_config sysresetreq
  58 }
  59
  60 proc stm32g0x_default_reset_start {} {
  61         # Reset clock is HSI16 (16 MHz)
  62         adapter speed 2000
  63 }
  64
  65 proc stm32g0x_default_examine_end {} {
  66         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
  67         mmw 0x40015804 0x00000006 0
  68
  69         # Stop watchdog counters during halt
  70         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  71         mmw 0x40015808 0x00001800 0
  72 }
  73
  74 proc stm32g0x_default_reset_init {} {
  75         # Increase clock to 64 Mhz
  76         mmw 0x40022000 0x00000002 0x00000005    ;# FLASH_ACR: Latency = 2
  77         mww 0x4002100C 0x30000802                               ;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
  78         mmw 0x40021000 0x01000000 0x00000000    ;# RCC_CR |= PLLON
  79         mmw 0x40021008 0x00000002 0x00000005    ;# RCC_CFGR: SW=PLLRCLK
  80
  81         # Boost JTAG frequency
  82         adapter speed 4000
  83 }
  84
  85 # Default hooks
  86 $_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
  87 $_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
  88 $_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }