1 # script for stm32f7x family
4 # stm32f7 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32f7x
17 # Work-area is a space in RAM used for flash programming
18 # By default use 128kB
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x20000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 # See STM Document RM0385
31 # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
32 set _CPUTAPID 0x5ba00477
34 set _CPUTAPID 0x5ba02477
38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
39 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
42 jtag newtap $_CHIPNAME bs -irlen 5
45 set _TARGETNAME $_CHIPNAME.cpu
46 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
48 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
50 set _FLASHNAME $_CHIPNAME.flash
51 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
53 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
56 adapter_nsrst_delay 100
61 # use hardware reset, connect under reset
62 reset_config srst_only srst_nogate
65 # if srst is not fitted use SYSRESETREQ to
66 # perform a soft reset
67 cortex_m reset_config sysresetreq
70 $_TARGETNAME configure -event examine-end {
71 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
72 mmw 0xE0042004 0x00000007 0
74 # Stop watchdog counters during halt
75 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
76 mmw 0xE0042008 0x00001800 0
79 $_TARGETNAME configure -event trace-config {
80 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
81 # change this value accordingly to configure trace pins
83 mmw 0xE0042004 0x00000020 0
86 $_TARGETNAME configure -event reset-init {
87 # If the HSE was previously enabled and the external clock source
88 # disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
89 # properly switched back to HSI. This situation persists even over a system
90 # reset, including a pin reset via SRST. However, activating the clock
91 # security system will detect the problem and clear HSERDY to 0, which in
92 # turn allows the PLL to switch back to HSI properly. Since we just came
93 # out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
94 # have happened; in that case, activate the clock security system to clear
96 if {[mrw 0x40023800] & 0x00020000} {
97 mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
98 sleep 10 ;# Wait for CSS to fire, if it wants to
99 mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
100 mww 0x4002380C 0x00800000 ;# RCC_CIR = CSSC
101 sleep 1 ;# Wait for CSSF to clear
104 # If the clock security system fired, it will pend an NMI. A pending NMI
105 # will cause a bad time for any subsequent executing code, such as a
106 # programming algorithm.
107 if {[mrw 0xE000ED04] & 0x80000000} {
108 # ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be
109 # cleared by any normal means (such as ICSR or NVIC). It can only be
110 # cleared by entering the NMI handler or by resetting the processor.
111 echo "[target current]: Clock security system generated NMI. Clearing."
113 # Keep the old DEMCR value.
114 set old [mrw 0xE000EDFC]
116 # Enable vector catch on reset.
117 mww 0xE000EDFC 0x01000001
119 # Issue local reset via AIRCR.
120 mww 0xE000ED0C 0x05FA0001
122 # Restore old DEMCR value.
126 # Configure PLL to boost clock to HSI x 10 (160 MHz)
127 mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
128 mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency)
129 mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
130 sleep 10 ;# Wait for PLL to lock
131 mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
132 mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
134 # Boost SWD frequency
135 # Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
136 # suffers from DAP WAITs
138 [[target current] cget -dap] memaccess 16
144 $_TARGETNAME configure -event reset-start {
145 # Reduce speed since CPU speed will slow down to 16MHz with the reset
149 # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
150 # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
151 # makes the data access cacheable. This allows reading and writing data in the
152 # CPU cache from the debugger, which is far more useful than going straight to
153 # RAM when operating on typical variables, and is generally no worse when
154 # operating on special memory locations.
155 $_CHIPNAME.dap apcsw 0x08000000 0x08000000