tcl/target/stm32f7x.cfg

   1 # script for stm32f7x family
   2
   3 #
   4 # stm32f7 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f7x
  13 }
  14
  15    set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 128kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x20000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30       # See STM Document RM0385
  31       # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
  32       set _CPUTAPID 0x5ba00477
  33    } {
  34       set _CPUTAPID 0x5ba02477
  35    }
  36 }
  37
  38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  39 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  40
  41 if {[using_jtag]} {
  42    jtag newtap $_CHIPNAME bs -irlen 5
  43 }
  44
  45 set _TARGETNAME $_CHIPNAME.cpu
  46 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  47
  48 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  49
  50 set _FLASHNAME $_CHIPNAME.flash
  51 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
  52
  53 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
  54 adapter_khz 2000
  55
  56 adapter_nsrst_delay 100
  57 if {[using_jtag]} {
  58  jtag_ntrst_delay 100
  59 }
  60
  61 # use hardware reset, connect under reset
  62 reset_config srst_only srst_nogate
  63
  64 if {![using_hla]} {
  65    # if srst is not fitted use SYSRESETREQ to
  66    # perform a soft reset
  67    cortex_m reset_config sysresetreq
  68 }
  69
  70 $_TARGETNAME configure -event examine-end {
  71         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  72         mmw 0xE0042004 0x00000007 0
  73
  74         # Stop watchdog counters during halt
  75         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  76         mmw 0xE0042008 0x00001800 0
  77 }
  78
  79 $_TARGETNAME configure -event trace-config {
  80         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  81         # change this value accordingly to configure trace pins
  82         # assignment
  83         mmw 0xE0042004 0x00000020 0
  84 }
  85
  86 $_TARGETNAME configure -event reset-init {
  87         # If the HSE was previously enabled and the external clock source
  88         # disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
  89         # properly switched back to HSI. This situation persists even over a system
  90         # reset, including a pin reset via SRST. However, activating the clock
  91         # security system will detect the problem and clear HSERDY to 0, which in
  92         # turn allows the PLL to switch back to HSI properly. Since we just came
  93         # out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
  94         # have happened; in that case, activate the clock security system to clear
  95         # HSERDY.
  96         if {[mrw 0x40023800] & 0x00020000} {
  97                 mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
  98                 sleep 10                    ;# Wait for CSS to fire, if it wants to
  99                 mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
 100                 mww 0x4002380C 0x00800000   ;# RCC_CIR = CSSC
 101                 sleep 1                     ;# Wait for CSSF to clear
 102         }
 103
 104         # If the clock security system fired, it will pend an NMI. A pending NMI
 105         # will cause a bad time for any subsequent executing code, such as a
 106         # programming algorithm.
 107         if {[mrw 0xE000ED04] & 0x80000000} {
 108                 # ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be
 109                 # cleared by any normal means (such as ICSR or NVIC). It can only be
 110                 # cleared by entering the NMI handler or by resetting the processor.
 111                 echo "[target current]: Clock security system generated NMI. Clearing."
 112
 113                 # Keep the old DEMCR value.
 114                 set old [mrw 0xE000EDFC]
 115
 116                 # Enable vector catch on reset.
 117                 mww 0xE000EDFC 0x01000001
 118
 119                 # Issue local reset via AIRCR.
 120                 mww 0xE000ED0C 0x05FA0001
 121
 122                 # Restore old DEMCR value.
 123                 mww 0xE000EDFC $old
 124         }
 125
 126         # Configure PLL to boost clock to HSI x 10 (160 MHz)
 127         mww 0x40023804 0x08002808   ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
 128         mww 0x40023C00 0x00000107   ;# FLASH_ACR = PRFTBE | 7(Latency)
 129         mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
 130         sleep 10                    ;# Wait for PLL to lock
 131         mww 0x40023808 0x00009400   ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
 132         mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
 133
 134         # Boost SWD frequency
 135         # Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
 136         # suffers from DAP WAITs
 137         if {[using_jtag]} {
 138                 [[target current] cget -dap] memaccess 16
 139         } {
 140                 adapter_khz 8000
 141         }
 142 }
 143
 144 $_TARGETNAME configure -event reset-start {
 145         # Reduce speed since CPU speed will slow down to 16MHz with the reset
 146         adapter_khz 2000
 147 }