tcl/target/stm32f4x.cfg

   1 # script for stm32f4x family
   2
   3 #
   4 # stm32 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f4x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 64kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x10000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30       # See STM Document RM0090
  31       # Section 38.6.3 - corresponds to Cortex-M4 r0p1
  32       set _CPUTAPID 0x4ba00477
  33    } {
  34       set _CPUTAPID 0x2ba01477
  35    }
  36 }
  37
  38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  39
  40 if { [info exists BSTAPID] } {
  41    set _BSTAPID $BSTAPID
  42 } else {
  43   # See STM Document RM0090
  44   # Section 38.6.2
  45   # STM32F405xx/07xx and STM32F415xx/17xx
  46   set _BSTAPID1 0x06413041
  47   # STM32F42xxx and STM32F43xxx
  48   set _BSTAPID2 0x06419041
  49   # See STM Document RM0368 (Rev. 3)
  50   # STM32F401B/C
  51   set _BSTAPID3 0x06423041
  52   # STM32F401D/E
  53   set _BSTAPID4 0x06433041
  54   # See STM Document RM0383 (Rev 2)
  55   # STM32F411
  56   set _BSTAPID5 0x06431041
  57 }
  58
  59 if {[using_jtag]} {
  60  swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
  61      -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
  62      -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
  63 }
  64
  65 set _TARGETNAME $_CHIPNAME.cpu
  66 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  67
  68 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  69
  70 set _FLASHNAME $_CHIPNAME.flash
  71 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
  72
  73 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
  74 #
  75 # Since we may be running of an RC oscilator, we crank down the speed a
  76 # bit more to be on the safe side. Perhaps superstition, but if are
  77 # running off a crystal, we can run closer to the limit. Note
  78 # that there can be a pretty wide band where things are more or less stable.
  79 adapter_khz 2000
  80
  81 adapter_nsrst_delay 100
  82 if {[using_jtag]} {
  83  jtag_ntrst_delay 100
  84 }
  85
  86 reset_config srst_nogate
  87
  88 if {![using_hla]} {
  89    # if srst is not fitted use SYSRESETREQ to
  90    # perform a soft reset
  91    cortex_m reset_config sysresetreq
  92 }
  93
  94 $_TARGETNAME configure -event examine-end {
  95         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  96         mmw 0xE0042004 0x00000007 0
  97
  98         # Stop watchdog counters during halt
  99         # DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
 100         mww 0xE0042008 0x00001800
 101 }
 102
 103 $_TARGETNAME configure -event trace-config {
 104         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 105         # change this value accordingly to configure trace pins
 106         # assignment
 107         mmw 0xE0042004 0x00000020 0
 108 }