tcl/target/stm32f4x.cfg

   1 # script for stm32f4x family
   2
   3 #
   4 # stm32 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME stm32f4x
  12 }
  13
  14 if { [info exists ENDIAN] } {
  15    set _ENDIAN $ENDIAN
  16 } else {
  17    set _ENDIAN little
  18 }
  19
  20 # Work-area is a space in RAM used for flash programming
  21 # By default use 64kB
  22 if { [info exists WORKAREASIZE] } {
  23    set _WORKAREASIZE $WORKAREASIZE
  24 } else {
  25    set _WORKAREASIZE 0x10000
  26 }
  27
  28 #jtag scan chain
  29 if { [info exists CPUTAPID] } {
  30    set _CPUTAPID $CPUTAPID
  31 } else {
  32   # See STM Document RM0090
  33   # Section 38.6.3 - corresponds to Cortex-M4 r0p1
  34    set _CPUTAPID 0x4ba00477
  35 }
  36
  37 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  38
  39 if { [info exists BSTAPID] } {
  40    set _BSTAPID $BSTAPID
  41 } else {
  42   # See STM Document RM0090
  43   # Section 38.6.2
  44   # STM32F405xx/07xx and STM32F415xx/17xx
  45   set _BSTAPID1 0x06413041
  46   # STM32F42xxx and STM32F43xxx
  47   set _BSTAPID2 0x06419041
  48 }
  49
  50 if {[using_jtag]} {
  51  jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
  52         -expected-id $_BSTAPID2
  53 }
  54
  55 set _TARGETNAME $_CHIPNAME.cpu
  56 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  57
  58 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  59
  60 set _FLASHNAME $_CHIPNAME.flash
  61 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
  62
  63 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  64 #
  65 # Since we may be running of an RC oscilator, we crank down the speed a
  66 # bit more to be on the safe side. Perhaps superstition, but if are
  67 # running off a crystal, we can run closer to the limit. Note
  68 # that there can be a pretty wide band where things are more or less stable.
  69 adapter_khz 1000
  70
  71 adapter_nsrst_delay 100
  72 if {[using_jtag]} {
  73  jtag_ntrst_delay 100
  74 }
  75
  76 # if srst is not fitted use SYSRESETREQ to
  77 # perform a soft reset
  78 cortex_m reset_config sysresetreq