tcl/target/stm32f2x.cfg

   1 # script for stm32f2x family
   2
   3 #
   4 # stm32 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f2x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 64kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x10000
  23 }
  24
  25 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  26 #
  27 # Since we may be running of an RC oscilator, we crank down the speed a
  28 # bit more to be on the safe side. Perhaps superstition, but if are
  29 # running off a crystal, we can run closer to the limit. Note
  30 # that there can be a pretty wide band where things are more or less stable.
  31 adapter_khz 1000
  32
  33 adapter_nsrst_delay 100
  34 if {[using_jtag]} {
  35  jtag_ntrst_delay 100
  36 }
  37
  38 #jtag scan chain
  39 if { [info exists CPUTAPID] } {
  40    set _CPUTAPID $CPUTAPID
  41 } else {
  42    if { [using_jtag] } {
  43       # See STM Document RM0033
  44       # Section 32.6.3 - corresponds to Cortex-M3 r2p0
  45       set _CPUTAPID 0x4ba00477
  46    } {
  47       set _CPUTAPID 0x2ba01477
  48    }
  49 }
  50
  51 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  52
  53 if {[using_jtag]} {
  54         jtag newtap $_CHIPNAME bs -irlen 5
  55 }
  56
  57 set _TARGETNAME $_CHIPNAME.cpu
  58 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  59
  60 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  61
  62 set _FLASHNAME $_CHIPNAME.flash
  63 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
  64
  65 reset_config srst_nogate
  66
  67 if {![using_hla]} {
  68    # if srst is not fitted use SYSRESETREQ to
  69    # perform a soft reset
  70    cortex_m reset_config sysresetreq
  71 }
  72
  73 $_TARGETNAME configure -event examine-end {
  74         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
  75         mmw 0xE0042004 0x00000007 0
  76
  77         # Stop watchdog counters during halt
  78         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  79         mmw 0xE0042008 0x00001800 0
  80 }
  81
  82 $_TARGETNAME configure -event trace-config {
  83         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  84         # change this value accordingly to configure trace pins
  85         # assignment
  86         mmw 0xE0042004 0x00000020 0
  87 }