tcl/target/stm32f1x.cfg

   1 # script for stm32f1x family
   2
   3 #
   4 # stm32 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f1x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 4kB (as found on some STM32F100s)
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x1000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30       # See STM Document RM0008 Section 26.6.3
  31       set _CPUTAPID 0x3ba00477
  32    } {
  33       # this is the SW-DP tap id not the jtag tap id
  34       set _CPUTAPID 0x1ba01477
  35    }
  36 }
  37
  38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  39
  40 if { [info exists BSTAPID] } {
  41    # FIXME this never gets used to override defaults...
  42    set _BSTAPID $BSTAPID
  43 } else {
  44   # See STM Document RM0008
  45   # Section 29.6.2
  46   # Low density devices, Rev A
  47   set _BSTAPID1 0x06412041
  48   # Medium density devices, Rev A
  49   set _BSTAPID2 0x06410041
  50   # Medium density devices, Rev B and Rev Z
  51   set _BSTAPID3 0x16410041
  52   set _BSTAPID4 0x06420041
  53   # High density devices, Rev A
  54   set _BSTAPID5 0x06414041
  55   # Connectivity line devices, Rev A and Rev Z
  56   set _BSTAPID6 0x06418041
  57   # XL line devices, Rev A
  58   set _BSTAPID7 0x06430041
  59   # VL line devices, Rev A and Z In medium-density and high-density value line devices
  60   set _BSTAPID8 0x06420041
  61   # VL line devices, Rev A
  62   set _BSTAPID9 0x06428041
  63 }
  64
  65 if {[using_jtag]} {
  66  swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
  67         -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
  68         -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
  69         -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \
  70         -expected-id $_BSTAPID8 -expected-id $_BSTAPID9
  71 }
  72
  73 set _TARGETNAME $_CHIPNAME.cpu
  74 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
  75
  76 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  77
  78 # flash size will be probed
  79 set _FLASHNAME $_CHIPNAME.flash
  80 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
  81
  82 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  83 adapter_khz 1000
  84
  85 adapter_nsrst_delay 100
  86 if {[using_jtag]} {
  87  jtag_ntrst_delay 100
  88 }
  89
  90 reset_config srst_nogate
  91
  92 if {![using_hla]} {
  93     # if srst is not fitted use SYSRESETREQ to
  94     # perform a soft reset
  95     cortex_m reset_config sysresetreq
  96 }
  97
  98 $_TARGETNAME configure -event examine-end {
  99         # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
 100         #              DBG_STANDBY | DBG_STOP | DBG_SLEEP
 101         mmw 0xE0042004 0x00000307 0
 102 }
 103
 104 $_TARGETNAME configure -event trace-config {
 105         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 106         # change this value accordingly to configure trace pins
 107         # assignment
 108         mmw 0xE0042004 0x00000020 0
 109 }