tcl/target/stm32f1x.cfg

   1 # script for stm32f1x family
   2
   3 #
   4 # stm32 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f1x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 4kB (as found on some STM32F100s)
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x1000
  23 }
  24
  25 # Allow overriding the Flash bank size
  26 if { [info exists FLASH_SIZE] } {
  27     set _FLASH_SIZE $FLASH_SIZE
  28 } else {
  29     # autodetect size
  30     set _FLASH_SIZE 0
  31 }
  32
  33 #jtag scan chain
  34 if { [info exists CPUTAPID] } {
  35    set _CPUTAPID $CPUTAPID
  36 } else {
  37    if { [using_jtag] } {
  38       # See STM Document RM0008 Section 26.6.3
  39       set _CPUTAPID 0x3ba00477
  40    } {
  41       # this is the SW-DP tap id not the jtag tap id
  42       set _CPUTAPID 0x1ba01477
  43    }
  44 }
  45
  46 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  47 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  48
  49 if {[using_jtag]} {
  50    jtag newtap $_CHIPNAME bs -irlen 5
  51 }
  52
  53 set _TARGETNAME $_CHIPNAME.cpu
  54 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  55
  56 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  57
  58 # flash size will be probed
  59 set _FLASHNAME $_CHIPNAME.flash
  60 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
  61
  62 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  63 adapter_khz 1000
  64
  65 adapter_nsrst_delay 100
  66 if {[using_jtag]} {
  67  jtag_ntrst_delay 100
  68 }
  69
  70 reset_config srst_nogate
  71
  72 if {![using_hla]} {
  73     # if srst is not fitted use SYSRESETREQ to
  74     # perform a soft reset
  75     cortex_m reset_config sysresetreq
  76 }
  77
  78 $_TARGETNAME configure -event examine-end {
  79         # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
  80         #              DBG_STANDBY | DBG_STOP | DBG_SLEEP
  81         mmw 0xE0042004 0x00000307 0
  82 }
  83
  84 $_TARGETNAME configure -event trace-config {
  85         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
  86         # change this value accordingly to configure trace pins
  87         # assignment
  88         mmw 0xE0042004 0x00000020 0
  89 }