tcl/target/stm32f0x.cfg

   1 # script for stm32f0x family
   2
   3 #
   4 # stm32 devices support SWD transports only.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f0x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 4kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x1000
  23 }
  24
  25 # Allow overriding the Flash bank size
  26 if { [info exists FLASH_SIZE] } {
  27         set _FLASH_SIZE $FLASH_SIZE
  28 } else {
  29         # autodetect size
  30         set _FLASH_SIZE 0
  31 }
  32
  33 #jtag scan chain
  34 if { [info exists CPUTAPID] } {
  35    set _CPUTAPID $CPUTAPID
  36 } else {
  37   # See STM Document RM0091
  38   # Section 29.5.3
  39    set _CPUTAPID 0x0bb11477
  40 }
  41
  42 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  43 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  44
  45 set _TARGETNAME $_CHIPNAME.cpu
  46 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  47
  48 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  49
  50 # flash size will be probed
  51 set _FLASHNAME $_CHIPNAME.flash
  52 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
  53
  54 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
  55 adapter_khz 1000
  56
  57 adapter_nsrst_delay 100
  58
  59 reset_config srst_nogate
  60
  61 if {![using_hla]} {
  62    # if srst is not fitted use SYSRESETREQ to
  63    # perform a soft reset
  64    cortex_m reset_config sysresetreq
  65 }
  66
  67 proc stm32f0x_default_reset_start {} {
  68         # Reset clock is HSI (8 MHz)
  69         adapter_khz 1000
  70 }
  71
  72 proc stm32f0x_default_examine_end {} {
  73         # Enable debug during low power modes (uses more power)
  74         mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
  75
  76         # Stop watchdog counters during halt
  77         mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
  78 }
  79
  80 proc stm32f0x_default_reset_init {} {
  81         # Configure PLL to boost clock to HSI x 6 (48 MHz)
  82         mww 0x40021004 0x00100000   ;# RCC_CFGR = PLLMUL[2]
  83         mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
  84         mww 0x40022000 0x00000011   ;# FLASH_ACR = PRFTBE | LATENCY[0]
  85         sleep 10                    ;# Wait for PLL to lock
  86         mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
  87
  88         # Boost JTAG frequency
  89         adapter_khz 8000
  90 }
  91
  92 # Default hooks
  93 $_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
  94 $_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
  95 $_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }