tcl/target/stellaris.cfg

   1 # TI/Luminary Stellaris LM3S chip family
   2
   3 # Luminary chips support both JTAG and SWD transports.
   4 # Adapt based on what transport is active.
   5 source [find target/swj-dp.tcl]
   6
   7 # For now we ignore the SPI and UART options, which
   8 # are usable only for ISP style initial flash programming.
   9
  10 if { [info exists CHIPNAME] } {
  11    set  _CHIPNAME $CHIPNAME
  12 } else {
  13    set  _CHIPNAME lm3s
  14 }
  15
  16 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
  17 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
  18 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
  19 # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
  20 # ... we'll ignore the JTAG version field, rather than list every
  21 # chip revision that turns up.
  22 if { [info exists CPUTAPID ] } {
  23    set _CPUTAPID $CPUTAPID
  24 } else {
  25    set _CPUTAPID 0x0ba00477
  26 }
  27
  28 # SWD DAP, and JTAG TAP, take same params for now;
  29 # ... even though SWD ignores all except TAPID, and
  30 # JTAG shouldn't need anything more then irlen. (and TAPID).
  31 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
  32         -expected-id $_CPUTAPID -ignore-version
  33
  34 if { [info exists WORKAREASIZE ] } {
  35    set _WORKAREASIZE $WORKAREASIZE
  36 } else {
  37    # default to 8K working area
  38    set _WORKAREASIZE 0x2000
  39 }
  40
  41 set _TARGETNAME $_CHIPNAME.cpu
  42 target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
  43
  44 # 8K working area at base of ram, not backed up
  45 #
  46 # NOTE:  you may need or want to reconfigure the work area;
  47 # some parts have just 6K, and you may want to use other
  48 # addresses (at end of mem not beginning) or back it up.
  49 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  50
  51 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
  52 # LM3S parts don't support RTCK
  53 #
  54 # NOTE:  this may be increased by a reset-init handler, after it
  55 # configures and enables the PLL.  Or you might need to decrease
  56 # this, if you're using a slower clock.
  57 adapter_khz 500
  58
  59 source [find mem_helper.tcl]
  60
  61 $_TARGETNAME configure -event reset-start {
  62         adapter_khz 500
  63
  64         #
  65         # When nRST is asserted on most Stellaris devices, it clears some of
  66         # the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
  67         # and OpenOCD depends on those TRMs.  So we won't use SRST on those
  68         # chips.  (Only power-on reset should affect debug state, beyond a
  69         # few specified bits; not the chip's nRST input, wired to SRST.)
  70         #
  71         # REVISIT current errata specs don't seem to cover this issue.
  72         # Do we have more details than this email?
  73         #   https://lists.berlios.de/pipermail
  74         #       /openocd-development/2008-August/003065.html
  75         #
  76
  77         set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
  78         if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
  79                 # Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
  80                 cortex_m3 reset_config sysresetreq
  81         } else {
  82                 # Tempest and newer default to using NVIC VECTRESET
  83                 # this does mean a reset-init event handler is required to reset
  84                 # any peripherals
  85                 cortex_m3 reset_config vectreset
  86         }
  87 }
  88
  89 # flash configuration ... autodetects sizes, autoprobed
  90 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
  91