tcl/target/stellaris.cfg

   1 # TI/Luminary Stellaris LM3S chip family
   2
   3 # Some devices have errata in returning their device class.
   4 # DEVICECLASS is provided as a manual override
   5 # Manual setting of a device class of 0xff is not allowed
   6
   7 global _DEVICECLASS
   8
   9 if { [info exists DEVICECLASS] } {
  10    set _DEVICECLASS $DEVICECLASS
  11 } else {
  12    set _DEVICECLASS 0xff
  13 }
  14
  15 # Luminary chips support both JTAG and SWD transports.
  16 # Adapt based on what transport is active.
  17 source [find target/swj-dp.tcl]
  18
  19 # For now we ignore the SPI and UART options, which
  20 # are usable only for ISP style initial flash programming.
  21
  22 if { [info exists CHIPNAME] } {
  23    set _CHIPNAME $CHIPNAME
  24 } else {
  25    set _CHIPNAME lm3s
  26 }
  27
  28 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
  29 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
  30 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
  31 # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
  32 # CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
  33 # ... we'll ignore the JTAG version field, rather than list every
  34 # chip revision that turns up.
  35 if { [info exists CPUTAPID] } {
  36    set _CPUTAPID $CPUTAPID
  37 } else {
  38    set _CPUTAPID 0x0ba00477
  39 }
  40
  41 # SWD DAP, and JTAG TAP, take same params for now;
  42 # ... even though SWD ignores all except TAPID, and
  43 # JTAG shouldn't need anything more then irlen. (and TAPID).
  44 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
  45         -expected-id $_CPUTAPID -ignore-version
  46
  47 if { [info exists WORKAREASIZE] } {
  48    set _WORKAREASIZE $WORKAREASIZE
  49 } else {
  50    # default to 2K working area
  51    set _WORKAREASIZE 0x800
  52 }
  53
  54 set _TARGETNAME $_CHIPNAME.cpu
  55 target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
  56
  57 # 8K working area at base of ram, not backed up
  58 #
  59 # NOTE: you may need or want to reconfigure the work area;
  60 # some parts have just 6K, and you may want to use other
  61 # addresses (at end of mem not beginning) or back it up.
  62 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  63
  64 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
  65 # LM3S parts don't support RTCK
  66 #
  67 # NOTE: this may be increased by a reset-init handler, after it
  68 # configures and enables the PLL.  Or you might need to decrease
  69 # this, if you're using a slower clock.
  70 adapter_khz 500
  71
  72 source [find mem_helper.tcl]
  73
  74 proc reset_peripherals {family} {
  75
  76         source [find chip/ti/lm3s/lm3s.tcl]
  77
  78         echo "Resetting Core Peripherals"
  79
  80         # Disable the PLL and the system clock divider (nop if disabled)
  81         mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
  82         mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
  83
  84         # RCC and RCC2 to their reset values
  85         mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))]
  86         mww $SYSCTL_RCC2 0x07806810
  87         mww $SYSCTL_RCC 0x078e3ad1
  88
  89         # Reset the deep sleep clock configuration register
  90         mww $SYSCTL_DSLPCLKCFG 0x07800000
  91
  92         # Reset the clock gating registers
  93         mww $SYSCTL_RCGC0 0x00000040
  94         mww $SYSCTL_RCGC1 0
  95         mww $SYSCTL_RCGC2 0
  96         mww $SYSCTL_SCGC0 0x00000040
  97         mww $SYSCTL_SCGC1 0
  98         mww $SYSCTL_SCGC2 0
  99         mww $SYSCTL_DCGC0 0x00000040
 100         mww $SYSCTL_DCGC1 0
 101         mww $SYSCTL_DCGC2 0
 102
 103         # Reset the remaining SysCtl registers
 104         mww $SYSCTL_PBORCTL 0
 105         mww $SYSCTL_IMC 0
 106         mww $SYSCTL_GPIOHBCTL 0
 107         mww $SYSCTL_MOSCCTL 0
 108         mww $SYSCTL_PIOSCCAL 0
 109         mww $SYSCTL_I2SMCLKCFG 0
 110
 111         # Reset the peripherals
 112         mww $SYSCTL_SRCR0 0xffffffff
 113         mww $SYSCTL_SRCR1 0xffffffff
 114         mww $SYSCTL_SRCR2 0xffffffff
 115         mww $SYSCTL_SRCR0 0
 116         mww $SYSCTL_SRCR1 0
 117         mww $SYSCTL_SRCR2 0
 118
 119         # Clear any pending SysCtl interrupts
 120         mww $SYSCTL_MISC 0xffffffff
 121
 122         # Wait for any pending flash operations to complete
 123         while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 }
 124         while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 }
 125
 126         # Reset the flash controller registers
 127         mww $FLASH_FMA 0
 128         mww $FLASH_FCIM 0
 129         mww $FLASH_FCMISC 0xffffffff
 130         mww $FLASH_FWBVAL 0
 131 }
 132
 133 $_TARGETNAME configure -event reset-start {
 134         adapter_khz 500
 135
 136         #
 137         # When nRST is asserted on most Stellaris devices, it clears some of
 138         # the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 139         # and OpenOCD depends on those TRMs.  So we won't use SRST on those
 140         # chips.  (Only power-on reset should affect debug state, beyond a
 141         # few specified bits; not the chip's nRST input, wired to SRST.)
 142         #
 143         # REVISIT current errata specs don't seem to cover this issue.
 144         # Do we have more details than this email?
 145         #   https://lists.berlios.de/pipermail
 146         #       /openocd-development/2008-August/003065.html
 147         #
 148
 149         global _DEVICECLASS
 150
 151         if {$_DEVICECLASS != 0xff} {
 152            set device_class $_DEVICECLASS
 153         } else {
 154            set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
 155         }
 156
 157         if {$device_class == 0 || $device_class == 1 ||
 158                 $device_class == 3 || $device_class == 5} {
 159                 # Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
 160                 cortex_m reset_config sysresetreq
 161         } else {
 162                 # Tempest and Firestorm default to using NVIC VECTRESET
 163                 # peripherals will need reseting manually, see proc reset_peripherals
 164                 cortex_m reset_config vectreset
 165
 166                 # reset peripherals, based on code in
 167                 # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
 168                 reset_peripherals $device_class
 169         }
 170 }
 171
 172 # flash configuration ... autodetects sizes, autoprobed
 173 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME