tcl/target/renesas_rcar_gen3.cfg

   1 # Renesas R-Car Generation 3 SOCs
   2 # - There are a combination of Cortex-A57s, Cortex-A53s, and Cortex-R7 for each Gen3 SOC
   3 # - Each SOC can boot through any of the, up to 3, core types that it has
   4 #   e.g. H3 can boot through Cortex-A57, Cortex-A53, or Cortex-R7
   5
   6 # Supported Gen3 SOCs and their cores:
   7 #  H3: Cortex-A57 x 4, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
   8 # M3W: Cortex-A57 x 2, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
   9 # M3N: Cortex-A57 x 2,                 Cortex-R7 x 2 (Lock-Step)
  10 # V3H:                 Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
  11 # V3M:                 Cortex-A53 x 2, Cortex-R7 x 2 (Lock-Step)
  12 #  E3:                 Cortex-A53 x 1, Cortex-R7 x 2 (Lock-Step)
  13 #  D3:                 Cortex-A53 x 1
  14
  15 # Usage:
  16 # There are 2 configuration options:
  17 # SOC:       Selects the supported SOC. (Default 'H3')
  18 # BOOT_CORE: Selects the booting core. 'CA57', 'CA53', or 'CR7'
  19 #            Defaults to 'CA57' if the SOC has one, else defaults to 'CA53'
  20
  21 if { [info exists SOC] } {
  22         set _soc $SOC
  23 } else {
  24         set _soc H3
  25 }
  26
  27 # Set configuration for each SOC and the default 'BOOT_CORE'
  28 switch $_soc {
  29         H3 {
  30                 set _CHIPNAME r8a77950
  31                 set _num_ca57 4
  32                 set _num_ca53 4
  33                 set _num_cr7 1
  34                 set _boot_core CA57
  35         }
  36         M3W {
  37                 set _CHIPNAME r8a77960
  38                 set _num_ca57 2
  39                 set _num_ca53 4
  40                 set _num_cr7 1
  41                 set _boot_core CA57
  42         }
  43         M3N {
  44                 set _CHIPNAME r8a77965
  45                 set _num_ca57 2
  46                 set _num_ca53 4
  47                 set _num_cr7 1
  48                 set _boot_core CA57
  49         }
  50         V3H {
  51                 set _CHIPNAME r8a77970
  52                 set _num_ca57 0
  53                 set _num_ca53 4
  54                 set _num_cr7 1
  55                 set _boot_core CA53
  56         }
  57         V3M {
  58                 set _CHIPNAME r8a77980
  59                 set _num_ca57 0
  60                 set _num_ca53 2
  61                 set _num_cr7 1
  62                 set _boot_core CA53
  63         }
  64         E3 {
  65                 set _CHIPNAME r8a77990
  66                 set _num_ca57 0
  67                 set _num_ca53 1
  68                 set _num_cr7 1
  69                 set _boot_core CA53
  70         }
  71         D3 {
  72                 set _CHIPNAME r8a77995
  73                 set _num_ca57 0
  74                 set _num_ca53 1
  75                 set _num_cr7 0
  76                 set _boot_core CA53
  77         }
  78         default {
  79                 echo "'$_soc' is invalid!"
  80         }
  81 }
  82
  83 # If configured, override the default 'CHIPNAME'
  84 if { [info exists CHIPNAME] } {
  85         set _CHIPNAME $CHIPNAME
  86 }
  87
  88 # If configured, override the default 'BOOT_CORE'
  89 if { [info exists BOOT_CORE] } {
  90         set _boot_core $BOOT_CORE
  91 }
  92
  93 if { [info exists DAP_TAPID] } {
  94         set _DAP_TAPID $DAP_TAPID
  95 } else {
  96         set _DAP_TAPID 0x5ba00477
  97 }
  98
  99 echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s)"
 100 echo "\tBoot Core - $_boot_core\n"
 101
 102 set _DAPNAME $_CHIPNAME.dap
 103
 104 # TAP and DAP
 105 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
 106 dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
 107
 108 set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
 109 set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
 110 set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
 111 set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
 112 set  CR7_DBGBASE 0x80910000
 113 set  CR7_CTIBASE 0x80918000
 114
 115 set smp_targets ""
 116
 117 proc setup_a5x {core_name dbgbase ctibase num boot} {
 118         global _CHIPNAME
 119         global _DAPNAME
 120         global smp_targets
 121         for { set _core 0 } { $_core < $num } { incr _core } {
 122                 set _TARGETNAME $_CHIPNAME.$core_name.$_core
 123                 set _CTINAME $_TARGETNAME.cti
 124                 cti create $_CTINAME -dap $_DAPNAME -ap-num 1 \
 125                         -ctibase [lindex $ctibase $_core]
 126                 set _command "target create $_TARGETNAME aarch64 -dap $_DAPNAME \
 127                         -ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME"
 128                 if { $_core == 0  && $boot == 1 } {
 129                         set _targets "$_TARGETNAME"
 130                 } else {
 131                         set _command "$_command -defer-examine"
 132                 }
 133                 set smp_targets "$smp_targets $_TARGETNAME"
 134                 eval $_command
 135         }
 136 }
 137
 138 proc setup_cr7 {dbgbase ctibase boot} {
 139         global _CHIPNAME
 140         global _DAPNAME
 141         set _TARGETNAME $_CHIPNAME.r7
 142         set _CTINAME $_TARGETNAME.cti
 143         cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -ctibase $ctibase
 144         set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
 145                 -ap-num 1 -dbgbase $dbgbase"
 146         if { $boot == 1 } {
 147                 set _targets "$_TARGETNAME"
 148         } else {
 149                 set _command "$_command -defer-examine"
 150         }
 151         eval $_command
 152 }
 153
 154 # Organize target list based on the boot core
 155 if { [string equal $_boot_core CA57] } {
 156         setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
 157         setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
 158         setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 0
 159 } elseif { [string equal $_boot_core CA53] } {
 160         setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
 161         setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
 162         setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 0
 163 } else {
 164         setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 1
 165         setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
 166         setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
 167 }
 168
 169 eval "target smp $smp_targets"