tcl/target/qualcomm_qca4531.cfg

   1 # The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable
   2 # Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT).
   3 #
   4 # Product page:
   5 # https://www.qualcomm.com/products/qca4531
   6 #
   7 # Notes:
   8 # - MIPS Processor ID (PRId): 0x00019374
   9 # - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
  10 #   operating at up to 650 MHz
  11 # - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up
  12 #   to 300 MHz
  13 # - TRST is not available.
  14 # - EJTAG PrRst signal is not supported
  15 # - RESET_L pin B56 on the SoC will reset internal JTAG logic.
  16 #
  17 # Pins related for debug and bootstrap:
  18 # Name          Pin             Description
  19 #   JTAG
  20 # JTAG_TCK      GPIO0, (A27)    Software configurable, default JTAG
  21 # JTAG_TDI      GPIO1, (B23)    Software configurable, default JTAG
  22 # JTAG_TDO      GPIO2, (A28)    Software configurable, default JTAG
  23 # JTAG_TMS      GPIO3, (A29)    Software configurable, default JTAG
  24 #   Reset
  25 # RESET_L       -, (B56)        Input only
  26 # SYS_RST_L     GPIO17, (A79)   Output reset request or GPIO
  27 #   Bootstrap
  28 # JTAG_MODE     GPIO16, (A78)   0 - JTAG (Default); 1 - EJTAG
  29 # DDR_SELECT    GPIO10, (A57)   0 - DDR2; 1 - DDR1
  30 #   UART
  31 # UART0_SOUT    GPIO10, (A57)
  32 # UART0_SIN     GPIO9, (B49)
  33
  34 # Per default we need to use "none" variant to be able properly "reset init"
  35 # or "reset halt" the CPU.
  36 reset_config none srst_pulls_trst
  37
  38 # For SRST based variant we still need proper timings.
  39 # For ETH part the reset should be asserted at least for 10ms
  40 # Since there is no other information let's take 100ms to be sure.
  41 adapter_nsrst_assert_width 100
  42
  43 # according to the SoC documentation it should take at least 5ms from
  44 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
  45 # to live.
  46 adapter_nsrst_delay 8
  47
  48 if { [info exists CHIPNAME] } {
  49         set _CHIPNAME $_CHIPNAME
  50 } else {
  51         set _CHIPNAME qca4531
  52 }
  53
  54 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
  55
  56 set _TARGETNAME $_CHIPNAME.cpu
  57 target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
  58
  59 # provide watchdog helper.
  60 proc disable_watchdog { } {
  61         mww 0xb8060008 0x0
  62 }
  63
  64 $_TARGETNAME configure -event halted { disable_watchdog }
  65
  66 # Since PrRst is not supported and SRST will reset complete chip
  67 # with JTAG engine, we need to reset CPU from CPU itself.
  68 $_TARGETNAME configure -event reset-assert-pre {
  69         halt
  70 }
  71
  72 $_TARGETNAME configure -event reset-assert {
  73         catch "mww 0xb806001C 0x01000000"
  74 }
  75
  76 # To be able to trigger complete chip reset, in case JTAG is blocked
  77 # or CPU not responding, we still can use this helper.
  78 proc full_reset { } {
  79         reset_config srst_only
  80         reset
  81         halt
  82         reset_config none
  83 }
  84
  85 # Section with helpers which can be used by boards
  86 proc qca4531_ddr2_550_550_init {} {
  87         # Clear reset flags for different SoC components
  88         mww 0xb806001c 0xfeceffff
  89         mww 0xb806001c 0xeeceffff
  90         mww 0xb806001c 0xe6ceffff
  91
  92         # PMU configurations
  93         # Internal Switcher
  94         mww 0xb8116c40 0x633c8176
  95         # Increase the DDR voltage
  96         mww 0xb8116c44 0x10200000
  97         # XTAL Configurations
  98         mww 0xb81162c0 0x4b962100
  99         mww 0xb81162c4 0x480
 100         mww 0xb81162c8 0x04000144
 101         # Recommended PLL configurations
 102         mww 0xb81161c4 0x54086000
 103         mww 0xb8116244 0x54086000
 104
 105         # PLL init
 106         mww 0xb8050008 0x0131001c
 107         mww 0xb8050000 0x40001580
 108         mww 0xb8050004 0x40015800
 109         mww 0xb8050008 0x0131001c
 110         mww 0xb8050000 0x00001580
 111         mww 0xb8050004 0x00015800
 112         mww 0xb8050008 0x01310000
 113         mww 0xb8050044 0x781003ff
 114         mww 0xb8050048 0x003c103f
 115
 116         # DDR2 init
 117         mww 0xb8000108 0x401f0042
 118         mww 0xb80000b8 0x0000166d
 119         mww 0xb8000000 0xcfaaf33b
 120         mww 0xb800015c 0x0000000f
 121         mww 0xb8000004 0xa272efa8
 122         mww 0xb8000018 0x0000ffff
 123         mww 0xb80000c4 0x74444444
 124         mww 0xb80000c8 0x00000444
 125         mww 0xb8000004 0xa210ee28
 126         mww 0xb8000004 0xa2b2e1a8
 127         mww 0xb8000010 0x8
 128         mww 0xb80000bc 0x0
 129         mww 0xb8000010 0x10
 130         mww 0xb80000c0 0x0
 131         mww 0xb8000010 0x40
 132         mww 0xb800000c 0x2
 133         mww 0xb8000010 0x2
 134         mww 0xb8000008 0xb43
 135         mww 0xb8000010 0x1
 136         mww 0xb8000010 0x8
 137         mww 0xb8000010 0x4
 138         mww 0xb8000010 0x4
 139         mww 0xb8000008 0xa43
 140         mww 0xb8000010 0x1
 141         mww 0xb800000c 0x382
 142         mww 0xb8000010 0x2
 143         mww 0xb800000c 0x402
 144         mww 0xb8000010 0x2
 145         mww 0xb8000014 0x40be
 146         mww 0xb800001C 0x20
 147         mww 0xb8000020 0x20
 148         mww 0xb80000cc 0xfffff
 149
 150         # UART GPIO programming
 151         mww 0xb8040000 0xff30b
 152         mww 0xb8040044 0x908
 153         mww 0xb8040034 0x160000
 154 }