tcl/target/pxa255.cfg

   1 if { [info exists CHIPNAME] } {
   2    set  _CHIPNAME $CHIPNAME
   3 } else {
   4    set  _CHIPNAME pxa255
   5 }
   6
   7 if { [info exists ENDIAN] } {
   8    set  _ENDIAN $ENDIAN
   9 } else {
  10    set  _ENDIAN little
  11 }
  12
  13 if { [info exists CPUTAPID ] } {
  14    set _CPUTAPID $CPUTAPID
  15 } else {
  16   # force an error till we get a good number
  17    set _CPUTAPID 0xffffffff
  18 }
  19
  20 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
  21
  22 jtag_nsrst_delay 200
  23 jtag_ntrst_delay 200
  24 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
  25 target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255
  26 $_TARGETNAME configure -event reset-init {
  27         xscale cp15   15      0x00002001  #Enable CP0 and CP13 access
  28         #
  29         # setup GPIO
  30         #
  31         mww    0x40E00018  0x00008000  #CPSR0
  32         sleep   20
  33         mww    0x40E0001C  0x00000002  #GPSR1
  34         sleep   20
  35         mww    0x40E00020  0x00000008  #GPSR2
  36         sleep   20
  37         mww    0x40E0000C  0x00008000  #GPDR0
  38         sleep   20
  39         mww    0x40E00054  0x80000000  #GAFR0_L
  40         sleep   20
  41         mww    0x40E00058  0x00188010  #GAFR0_H
  42         sleep   20
  43         mww    0x40E0005C  0x60908018  #GAFR1_L
  44         sleep   20
  45         mww    0x40E0000C  0x0280E000  #GPDR0
  46         sleep   20
  47         mww    0x40E00010  0x821C88B2  #GPDR1
  48         sleep   20
  49         mww    0x40E00014  0x000F03DB  #GPDR2
  50         sleep   20
  51         mww    0x40E00000  0x000F03DB  #GPLR0
  52         sleep   20
  53
  54
  55         mww    0x40F00004  0x00000020  #PSSR
  56         sleep   20
  57
  58         #
  59         # setup memory controller
  60         #
  61         mww    0x48000008  0x01111998  #MSC0
  62         sleep   20
  63         mww    0x48000010  0x00047ff0  #MSC2
  64         sleep   20
  65         mww    0x48000014  0x00000000  #MECR
  66         sleep   20
  67         mww    0x48000028  0x00010504  #MCMEM0
  68         sleep   20
  69         mww    0x4800002C  0x00010504  #MCMEM1
  70         sleep   20
  71         mww    0x48000030  0x00010504  #MCATT0
  72         sleep   20
  73         mww    0x48000034  0x00010504  #MCATT1
  74         sleep   20
  75         mww    0x48000038  0x00004715  #MCIO0
  76         sleep   20
  77         mww    0x4800003C  0x00004715  #MCIO1
  78         sleep   20
  79         #
  80         mww    0x48000004  0x03CA4018  #MDREF
  81         sleep   20
  82         mww    0x48000004  0x004B4018  #MDREF
  83         sleep   20
  84         mww    0x48000004  0x000B4018  #MDREF
  85         sleep   20
  86         mww    0x48000004  0x000BC018  #MDREF
  87         sleep   20
  88         mww    0x48000000  0x00001AC8  #MDCNFG
  89         sleep   20
  90
  91         sleep   20
  92
  93         mww    0x48000000  0x00001AC9  #MDCNFG
  94         sleep   20
  95         mww    0x48000040  0x00000000  #MDMRS
  96         sleep   20
  97 }
  98
  99 reset_config trst_and_srst
 100
 101
 102
 103 #xscale debug_handler 0  0xFFFF0800      # debug handler base address
 104