psoc6: Run flash algorithm asynchronously to improve performance
[openocd.git] / tcl / target / psoc6.cfg
1 #
2 # Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
3 # PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
4 # the same Flash/RAM/MMIO address space.
5 #
6
7 source [find target/swj-dp.tcl]
8
9 adapter_khz 1000
10
11 global _CHIPNAME
12 if { [info exists CHIPNAME] } {
13         set _CHIPNAME $CHIPNAME
14 } else {
15         set _CHIPNAME psoc6
16 }
17
18 global TARGET
19 set TARGET $_CHIPNAME.cpu
20
21 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
22 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
23
24 # Is CM0 Debugging enabled ?
25 global _ENABLE_CM0
26 if { [info exists ENABLE_CM0] } {
27         set _ENABLE_CM0 $ENABLE_CM0
28 } else {
29         set _ENABLE_CM0 1
30 }
31
32 # Is CM4 Debugging enabled ?
33 global _ENABLE_CM4
34 if { [info exists ENABLE_CM4] } {
35         set _ENABLE_CM4 $ENABLE_CM4
36 } else {
37         set _ENABLE_CM4 1
38 }
39
40 global _WORKAREASIZE_CM0
41 if { [info exists WORKAREASIZE_CM0] } {
42         set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
43 } else {
44         set _WORKAREASIZE_CM0 0x4000
45 }
46
47 global _WORKAREASIZE_CM4
48 if { [info exists WORKAREASIZE_CM4] } {
49         set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
50 } else {
51         set _WORKAREASIZE_CM4 0x4000
52 }
53
54 global _WORKAREAADDR_CM0
55 if { [info exists WORKAREAADDR_CM0] } {
56         set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
57 } else {
58         set _WORKAREAADDR_CM0 0x08000000
59 }
60
61 global _WORKAREAADDR_CM4
62 if { [info exists WORKAREAADDR_CM4] } {
63         set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
64 } else {
65         set _WORKAREAADDR_CM4 0x08000000
66 }
67
68 proc init_reset { mode } {
69         global RESET_MODE
70         set RESET_MODE $mode
71
72         if {[using_jtag]} {
73                 jtag arp_init-reset
74         }
75 }
76
77 # Utility to make 'reset halt' work as reset;halt on a target
78 # It does not prevent running code after reset
79 proc psoc6_deassert_post { target } {
80         # PSoC6 cleared AP registers including TAR during reset
81         # Force examine to synchronize OpenOCD target status
82         $target arp_examine
83
84         global RESET_MODE
85         global TARGET
86
87         if { $RESET_MODE ne "run" } {
88                 $target arp_poll
89                 $target arp_poll
90                 set st [$target curstate]
91
92                 if { $st eq "reset" } {
93                         # we assume running state follows
94                         # if reset accidentally halts, waiting is useless
95                         catch { $target arp_waitstate running 100 }
96                         set st [$target curstate]
97                 }
98
99                 if { $st eq "running" } {
100                         echo "$target: Ran after reset and before halt..."
101                         if { $target eq "${TARGET}.cm0" } {
102                                 # Try to cleanly reset whole system
103                                 # and halt the CM0 at entry point
104                                 psoc6 reset_halt
105                                 $target arp_waitstate halted 100
106                         } else {
107                                 $target arp_halt
108                         }
109                 }
110         }
111 }
112
113 if { $_ENABLE_CM0 } {
114         target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
115         ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
116
117         flash bank main_flash_cm0               psoc6 0x10000000 0 0 0 ${TARGET}.cm0
118         flash bank work_flash_cm0               psoc6 0x14000000 0 0 0 ${TARGET}.cm0
119         flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 ${TARGET}.cm0
120         flash bank super_flash_nar_cm0  psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
121         flash bank super_flash_key_cm0  psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
122         flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
123
124         ${TARGET}.cm0 cortex_m reset_config sysresetreq
125         ${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
126 }
127
128 if { $_ENABLE_CM4 } {
129         target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
130         ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
131
132         flash bank main_flash_cm4               psoc6 0x10000000 0 0 0 ${TARGET}.cm4
133         flash bank work_flash_cm4               psoc6 0x14000000 0 0 0 ${TARGET}.cm4
134         flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 ${TARGET}.cm4
135         flash bank super_flash_nar_cm4  psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
136         flash bank super_flash_key_cm4  psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
137         flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
138
139         ${TARGET}.cm4 cortex_m reset_config vectreset
140         ${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
141 }
142
143 if { $_ENABLE_CM0 } {
144         # Use CM0+ by default on dual-core devices
145         targets ${TARGET}.cm0
146 }
147
148 if {[using_jtag]} {
149         swj_newdap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
150 }