tcl/target/pic32mx.cfg

   1 if { [info exists CHIPNAME] } {
   2    set _CHIPNAME $CHIPNAME
   3 } else {
   4    set _CHIPNAME pic32mx
   5 }
   6
   7 if { [info exists ENDIAN] } {
   8    set _ENDIAN $ENDIAN
   9 } else {
  10    set _ENDIAN little
  11 }
  12
  13 if { [info exists CPUTAPID] } {
  14    set _CPUTAPID $CPUTAPID
  15 } else {
  16    set _CPUTAPID 0x30938053
  17 }
  18
  19 # default working area is 16384
  20 if { [info exists WORKAREASIZE] } {
  21    set _WORKAREASIZE $WORKAREASIZE
  22 } else {
  23    set _WORKAREASIZE 0x4000
  24 }
  25
  26 adapter_nsrst_delay 100
  27 jtag_ntrst_delay 100
  28
  29 #jtag scan chain
  30 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
  31 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
  32
  33 set _TARGETNAME $_CHIPNAME.cpu
  34 target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
  35
  36 #
  37 # At reset the pic32mx does not allow code execution from RAM
  38 # we have to setup the BMX registers to allow this.
  39 # One limitation is that we loose the first 2k of RAM.
  40 #
  41
  42 global _PIC32MX_DATASIZE
  43 global _WORKAREASIZE
  44 set _PIC32MX_DATASIZE 0x800
  45 set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)]
  46
  47 $_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
  48 $_TARGETNAME configure -event reset-init {
  49         #
  50         # from reset the pic32 cannot execute code in ram - enable ram execution
  51         # minimum offset from start of ram is 2k
  52         #
  53         global _PIC32MX_DATASIZE
  54         global _WORKAREASIZE
  55
  56         # BMXCON        set 0 wait state option by clearing BMXWSDRM bit, bit 6
  57         mww 0xbf882000 0x001f0000
  58         # BMXDKPBA: 2k kernel data @ 0xa0000000
  59         mww 0xbf882010 $_PIC32MX_DATASIZE
  60         # BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
  61         mww 0xbf882020 $_WORKAREASIZE
  62         # BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
  63         mww 0xbf882030 $_WORKAREASIZE
  64
  65         #
  66         # Set system clock to 8Mhz if the default clock configuration is set
  67         #
  68
  69         # SYSKEY register, make sure OSCCON is locked
  70         mww 0xbf80f230 0x0
  71         # SYSKEY register, write unlock sequence
  72         mww 0xbf80f230 0xaa996655
  73         mww 0xbf80f230 0x556699aa
  74         # OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
  75         mww 0xbf80f004 0x07000000
  76         # SYSKEY register, relock OSCCON
  77         mww 0xbf80f230 0x0
  78 }
  79
  80 set _FLASHNAME $_CHIPNAME.flash0
  81 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
  82 # add virtual banks for kseg0 and kseg1
  83 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  84 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  85
  86 set _FLASHNAME $_CHIPNAME.flash1
  87 flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
  88 # add virtual banks for kseg0 and kseg1
  89 flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
  90 flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME