tcl/target/omap4430.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # OMAP4430
   4
   5 if { [info exists CHIPNAME] } {
   6         set _CHIPNAME $CHIPNAME
   7 } else {
   8         set _CHIPNAME omap4430
   9 }
  10
  11
  12 # Although the OMAP4430 supposedly has an ICEpick-D, only the
  13 # ICEpick-C router commands seem to work.
  14 # See http://processors.wiki.ti.com/index.php/ICEPICK
  15 source [find target/icepick.cfg]
  16
  17
  18 #
  19 # A9 DAP
  20 #
  21 if { [info exists DAP_TAPID] } {
  22         set _DAP_TAPID $DAP_TAPID
  23 } else {
  24         set _DAP_TAPID 0x3BA00477
  25 }
  26
  27 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
  28         -expected-id $_DAP_TAPID -disable
  29 jtag configure $_CHIPNAME.cpu -event tap-enable \
  30         "icepick_c_tapenable $_CHIPNAME.jrc 9"
  31
  32
  33 #
  34 # M3 DAPs, one per core
  35 #
  36 if { [info exists M3_DAP_TAPID] } {
  37         set _M3_DAP_TAPID $M3_DAP_TAPID
  38 } else {
  39         set _M3_DAP_TAPID 0x4BA00477
  40 }
  41
  42 jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
  43         -expected-id $_M3_DAP_TAPID -disable
  44 jtag configure $_CHIPNAME.m31 -event tap-enable \
  45         "icepick_c_tapenable $_CHIPNAME.jrc 5"
  46
  47 jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
  48         -expected-id $_M3_DAP_TAPID -disable
  49 jtag configure $_CHIPNAME.m30 -event tap-enable \
  50         "icepick_c_tapenable $_CHIPNAME.jrc 4"
  51
  52
  53 #
  54 # ICEpick-D JRC (JTAG route controller)
  55 #
  56 if { [info exists JRC_TAPID] } {
  57         set _JRC_TAPID $JRC_TAPID
  58 } else {
  59         set _JRC_TAPID  0x3b95c02f
  60         set _JRC_TAPID2 0x1b85202f
  61 }
  62
  63 # PandaBoard REV EA1 (PEAP platforms)
  64 if { [info exists JRC_TAPID2] } {
  65         set _JRC_TAPID2 $JRC_TAPID2
  66 } else {
  67         set _JRC_TAPID2 0x1b85202f
  68 }
  69
  70
  71
  72 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
  73         -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
  74
  75 # Required by ICEpick to power-up the debug domain
  76 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
  77
  78
  79 #
  80 # GDB target: Cortex-A9, using DAP
  81 #
  82 # The debugger can connect to either core of the A9, but currently
  83 # not both simultaneously.  Change -coreid to 1 to connect to the
  84 # second core.
  85 #
  86 set _TARGETNAME $_CHIPNAME.cpu
  87
  88 # APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
  89 # 0x80000000 is cpu0 coresight region
  90 #
  91 #
  92 # CORTEX_A8_PADDRDBG_CPU_SHIFT 13
  93 # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
  94
  95 set _coreid 0
  96 set _dbgbase [expr {0x80000000 | ($_coreid << 13)}]
  97 echo "Using dbgbase = [format 0x%x $_dbgbase]"
  98
  99 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 100 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
 101   -coreid 0 -dbgbase $_dbgbase
 102
 103 # SRAM: 56KiB at 0x4030.0000
 104 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 105
 106
 107 #
 108 # M3 targets, separate TAP/DAP for each core
 109 #
 110 dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
 111 dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
 112 target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
 113 target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
 114
 115
 116 # Once the JRC is up, enable our TAPs
 117 jtag configure $_CHIPNAME.jrc -event setup "
 118         jtag tapenable $_CHIPNAME.cpu
 119         jtag tapenable $_CHIPNAME.m30
 120         jtag tapenable $_CHIPNAME.m31
 121 "
 122
 123 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 124 # ourselves using PRM_RSTCTRL.  1 is a warm reset, 2 a cold reset.
 125 set PRM_RSTCTRL 0x4A307B00
 126 $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
 127 $_CHIPNAME.m30 configure -event reset-assert { }
 128 $_CHIPNAME.m31 configure -event reset-assert { }
 129
 130 # Soft breakpoints don't currently work due to broken cache handling
 131 gdb_breakpoint_override hard