tcl/target/omap3530.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # TI OMAP3530
   4 # http://focus.ti.com/docs/prod/folders/print/omap3530.html
   5 # Other OMAP3 chips remove DSP and/or the OpenGL support
   6
   7 if { [info exists CHIPNAME] } {
   8    set _CHIPNAME $CHIPNAME
   9 } else {
  10    set _CHIPNAME omap3530
  11 }
  12
  13 # ICEpick-C ... used to route Cortex, DSP, and more not shown here
  14 source [find target/icepick.cfg]
  15
  16 # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
  17 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
  18
  19 # Subsidiary TAP: CoreSight Debug Access Port (DAP)
  20 if { [info exists DAP_TAPID] } {
  21    set _DAP_TAPID $DAP_TAPID
  22 } else {
  23    set _DAP_TAPID 0x0b6d602f
  24 }
  25 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
  26         -expected-id $_DAP_TAPID -disable
  27 jtag configure $_CHIPNAME.cpu -event tap-enable \
  28         "icepick_c_tapenable $_CHIPNAME.jrc 3"
  29
  30 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  31 if { [info exists JRC_TAPID] } {
  32    set _JRC_TAPID $JRC_TAPID
  33 } else {
  34    set _JRC_TAPID 0x0b7ae02f
  35 }
  36 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
  37         -expected-id $_JRC_TAPID
  38
  39 # GDB target: Cortex-A8, using DAP
  40 set _TARGETNAME $_CHIPNAME.cpu
  41 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  42 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
  43
  44 # SRAM: 64K at 0x4020.0000; use the first 16K
  45 $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
  46
  47 ###################
  48
  49 # the reset sequence is event-driven
  50 # and kind of finicky...
  51
  52 # some TCK tycles are required to activate the DEBUG power domain
  53 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
  54
  55 # have the DAP "always" be active
  56 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
  57
  58 proc omap3_dbginit {target} {
  59      # General Cortex-A8 debug initialisation
  60      cortex_a dbginit
  61      # Enable DBGU signal for OMAP353x
  62      $target mww phys 0x5401d030 0x00002000
  63 }
  64
  65 # be absolutely certain the JTAG clock will work with the worst-case
  66 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
  67 # OK to speed up *after* PLL and clock tree setup.
  68 adapter speed 1000
  69 $_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
  70
  71 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
  72 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
  73 # would issue.  RST_DPLL3 (4) is a cold reset.
  74 set PRM_RSTCTRL 0x48307250
  75 $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
  76
  77 $_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"