tcl/target/omap3530.cfg

   1 # TI OMAP3530
   2 # http://focus.ti.com/docs/prod/folders/print/omap3530.html
   3 # Other OMAP3 chips remove DSP and/or the OpenGL support
   4
   5 if { [info exists CHIPNAME] } {
   6    set _CHIPNAME $CHIPNAME
   7 } else {
   8    set _CHIPNAME omap3530
   9 }
  10
  11 # ICEpick-C ... used to route Cortex, DSP, and more not shown here
  12 source [find target/icepick.cfg]
  13
  14 # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
  15 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
  16
  17 # Subsidiary TAP: CoreSight Debug Access Port (DAP)
  18 if { [info exists DAP_TAPID] } {
  19    set _DAP_TAPID $DAP_TAPID
  20 } else {
  21    set _DAP_TAPID 0x0b6d602f
  22 }
  23 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
  24         -expected-id $_DAP_TAPID -disable
  25 jtag configure $_CHIPNAME.cpu -event tap-enable \
  26         "icepick_c_tapenable $_CHIPNAME.jrc 3"
  27
  28 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  29 if { [info exists JRC_TAPID] } {
  30    set _JRC_TAPID $JRC_TAPID
  31 } else {
  32    set _JRC_TAPID 0x0b7ae02f
  33 }
  34 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
  35         -expected-id $_JRC_TAPID
  36
  37 # GDB target: Cortex-A8, using DAP
  38 set _TARGETNAME $_CHIPNAME.cpu
  39 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  40 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
  41
  42 # SRAM: 64K at 0x4020.0000; use the first 16K
  43 $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
  44
  45 ###################
  46
  47 # the reset sequence is event-driven
  48 # and kind of finicky...
  49
  50 # some TCK tycles are required to activate the DEBUG power domain
  51 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
  52
  53 # have the DAP "always" be active
  54 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
  55
  56 proc omap3_dbginit {target} {
  57      # General Cortex-A8 debug initialisation
  58      cortex_a dbginit
  59      # Enable DBGU signal for OMAP353x
  60      $target mww phys 0x5401d030 0x00002000
  61 }
  62
  63 # be absolutely certain the JTAG clock will work with the worst-case
  64 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
  65 # OK to speed up *after* PLL and clock tree setup.
  66 adapter speed 1000
  67 $_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
  68
  69 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
  70 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
  71 # would issue.  RST_DPLL3 (4) is a cold reset.
  72 set PRM_RSTCTRL 0x48307250
  73 $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
  74
  75 $_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"