target: restructure dap support
[openocd.git] / tcl / target / lpc4370.cfg
1 #
2 # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
3 #
4
5 adapter_khz 500
6
7 if { [info exists CHIPNAME] } {
8         set _CHIPNAME $CHIPNAME
9 } else {
10         set _CHIPNAME lpc4370
11 }
12
13 #
14 # M4 JTAG mode TAP
15 #
16 if { [info exists M4_JTAG_TAPID] } {
17         set _M4_JTAG_TAPID $M4_JTAG_TAPID
18 } else {
19         set _M4_JTAG_TAPID 0x4ba00477
20 }
21
22 #
23 # M4 SWD mode TAP
24 #
25 if { [info exists M4_SWD_TAPID] } {
26         set _M4_SWD_TAPID $M4_SWD_TAPID
27 } else {
28         set _M4_SWD_TAPID 0x2ba01477
29 }
30
31 source [find target/swj-dp.tcl]
32
33 if { [using_jtag] } {
34         set _M4_TAPID $_M4_JTAG_TAPID
35 } else {
36         set _M4_TAPID $_M4_SWD_TAPID
37 }
38
39 #
40 # M0 TAP
41 #
42 if { [info exists M0_JTAG_TAPID] } {
43         set _M0_JTAG_TAPID $M0_JTAG_TAPID
44 } else {
45         set _M0_JTAG_TAPID 0x0ba01477
46 }
47
48 swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
49                                 -expected-id $_M4_TAPID
50 dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
51 target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
52
53 # LPC4370 has 96+32 KB contiguous SRAM
54 if { [info exists WORKAREASIZE] } {
55         set _WORKAREASIZE $WORKAREASIZE
56 } else {
57         set _WORKAREASIZE 0x20000
58 }
59 $_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
60                         -work-area-size $_WORKAREASIZE -work-area-backup 0
61
62 if { [using_jtag] } {
63         jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \
64                                         -expected-id $_M0_JTAG_TAPID
65         jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
66                                         -expected-id $_M0_JTAG_TAPID
67
68         dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
69         dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
70         target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
71         target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
72
73         # 32+8+32 KB SRAM
74         $_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
75                                    -work-area-size 0x92000 -work-area-backup 0
76
77         # 16+2 KB M0 subsystem SRAM
78         $_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \
79                                    -work-area-size 0x4800 -work-area-backup 0
80
81         # Default to the Cortex-M4
82         targets $_CHIPNAME.m4
83 }
84
85 if { ![using_hla] } {
86         cortex_m reset_config vectreset
87 }