tcl/target/lpc2900.cfg

   1
   2 if { [info exists CHIPNAME] } {
   3     set _CHIPNAME $CHIPNAME
   4 } else {
   5     set _CHIPNAME lpc2900
   6 }
   7
   8 if { [info exists CPUTAPID] } {
   9     set _CPUTAPID $CPUTAPID
  10 } else {
  11     set _CPUTAPID 0x0596802B
  12 }
  13
  14 if { [info exists HAS_ETB] } {
  15 } else {
  16     # Set default (no ETB).
  17     # Show a warning, because this should have been configured explicitly.
  18     set HAS_ETB 0
  19     # TODO: warning?
  20 }
  21
  22 if { [info exists ETBTAPID] } {
  23     set _ETBTAPID $ETBTAPID
  24 } else {
  25     set _ETBTAPID 0x1B900F0F
  26 }
  27
  28 # TRST and SRST both exist, and can be controlled independently
  29 reset_config trst_and_srst separate
  30
  31 # Define the _TARGETNAME
  32 set _TARGETNAME $_CHIPNAME.cpu
  33
  34 # Include the ETB tap controller if asked for.
  35 # Has to be done manually for newer devices (not an "old" LPC2917/2919).
  36 if { $HAS_ETB == 1 } {
  37     # Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
  38     set HAS_ETB 0
  39
  40     # Add the ETB tap controller and the ARM9 core debug tap
  41     jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
  42     jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  43
  44     # Create the ".cpu" target
  45     target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
  46
  47     # Configure ETM and ETB
  48     etm config $_TARGETNAME 8 normal full etb
  49     etb config $_TARGETNAME $_CHIPNAME.etb
  50
  51 } else {
  52     # Add the ARM9 core debug tap
  53     jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  54
  55     # Create the ".cpu" target
  56     target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
  57 }
  58
  59 arm7_9 dbgrq enable
  60 arm7_9 dcc_downloads enable
  61
  62 # Flash bank configuration:
  63 # Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
  64 # Flash base address, total flash size, and number of sectors are all configured automatically.
  65 set _FLASHNAME $_CHIPNAME.flash
  66 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK