tcl/target/lpc17xx.cfg

   1 # Main file for NXP LPC17xx Cortex-M3
   2 #
   3 # !!!!!!
   4 #
   5 # This file should not be included directly, rather
   6 # by the lpc1751.cfg, lpc1752.cfg, etc. which set the
   7 # needed variables to the appropriate values.
   8 #
   9 # !!!!!!
  10
  11 # LPC17xx chips support both JTAG and SWD transports.
  12 # Adapt based on what transport is active.
  13 source [find target/swj-dp.tcl]
  14
  15 if { [info exists CHIPNAME] } {
  16         set _CHIPNAME $CHIPNAME
  17 } else {
  18         error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
  19 }
  20
  21 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
  22 # When board-specific code (reset-init handler or device firmware)
  23 # configures another oscillator and/or PLL0, set CCLK to match; if
  24 # you don't, then flash erase and write operations may misbehave.
  25 # (The ROM code doing those updates cares about core clock speed...)
  26 #
  27 # CCLK is the core clock frequency in KHz
  28 if { [info exists CCLK] } {
  29         set _CCLK $CCLK
  30 } else {
  31         set _CCLK 4000
  32 }
  33
  34 if { [info exists CPUTAPID] } {
  35         set _CPUTAPID $CPUTAPID
  36 } else {
  37         error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
  38 }
  39
  40 if { [info exists CPURAMSIZE] } {
  41   set _CPURAMSIZE $CPURAMSIZE
  42 } else {
  43         error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
  44 }
  45
  46 if { [info exists CPUROMSIZE] } {
  47   set _CPUROMSIZE $CPUROMSIZE
  48 } else {
  49         error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
  50 }
  51
  52 #delays on reset lines
  53 adapter_nsrst_delay 200
  54 jtag_ntrst_delay 200
  55
  56 #jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  57 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  58
  59 set _TARGETNAME $_CHIPNAME.cpu
  60 target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
  61
  62 # The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
  63 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
  64
  65 # The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
  66 # (including a boot loader which verifies the flash exception table's checksum).
  67 # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
  68 set _FLASHNAME $_CHIPNAME.flash
  69 flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
  70         lpc1700 $_CCLK calc_checksum
  71
  72 # Run with *real slow* clock by default since the
  73 # boot rom could have been playing with the PLL, so
  74 # we have no idea what clock the target is running at.
  75 adapter_khz 10
  76
  77 $_TARGETNAME configure -event reset-init {
  78         # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
  79         # "User Flash Mode" where interrupt vectors are _not_ remapped,
  80         # and reside in flash instead).
  81         #
  82         # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
  83         # Bit Symbol Value Description Reset
  84         # value
  85         # 0 MAP Memory map control. 0
  86         # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
  87         # 1 User mode. The on-chip Flash memory is mapped to address 0.
  88         # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
  89         #
  90         # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
  91
  92         mww 0x400FC040 0x01
  93 }