tcl/target/ixp42x.cfg

   1 #xscale ixp42x CPU
   2
   3 if { [info exists CHIPNAME] } {
   4    set _CHIPNAME $CHIPNAME
   5 } else {
   6    set _CHIPNAME ixp42x
   7 }
   8
   9 if { [info exists ENDIAN] } {
  10    set _ENDIAN $ENDIAN
  11 } else {
  12   # this defaults to a bigendian
  13    set _ENDIAN big
  14 }
  15
  16 if { [info exists CPUTAPID] } {
  17    set _CPUTAPID $CPUTAPID
  18 } else {
  19    set _CPUTAPID 0x19274013
  20 }
  21 set _CPUTAPID2 0x19275013
  22 set _CPUTAPID3 0x19277013
  23 set _CPUTAPID4 0x29274013
  24 set _CPUTAPID5 0x29275013
  25 set _CPUTAPID6 0x29277013
  26
  27 jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6
  28
  29 set _TARGETNAME $_CHIPNAME.cpu
  30 target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
  31
  32
  33 # register constants for IXP42x SDRAM controller
  34 global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
  35 global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
  36 set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD   0x0000
  37 set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD   0x0001
  38
  39 global IXP42x_SDRAM_CL3
  40 global IXP42x_SDRAM_CL2
  41 set IXP42x_SDRAM_CL3                    0x0008
  42 set IXP42x_SDRAM_CL2                    0x0000
  43
  44 global IXP42x_SDRAM_8MB_2Mx32_1BANK
  45 global IXP42x_SDRAM_16MB_2Mx32_2BANK
  46 global IXP42x_SDRAM_16MB_4Mx16_1BANK
  47 global IXP42x_SDRAM_32MB_4Mx16_2BANK
  48 global IXP42x_SDRAM_32MB_8Mx16_1BANK
  49 global IXP42x_SDRAM_64MB_8Mx16_2BANK
  50 global IXP42x_SDRAM_64MB_16Mx16_1BANK
  51 global IXP42x_SDRAM_128MB_16Mx16_2BANK
  52 global IXP42x_SDRAM_128MB_32Mx16_1BANK
  53 global IXP42x_SDRAM_256MB_32Mx16_2BANK
  54
  55 set IXP42x_SDRAM_8MB_2Mx32_1BANK        0x0030
  56 set IXP42x_SDRAM_16MB_2Mx32_2BANK       0x0031
  57 set IXP42x_SDRAM_16MB_4Mx16_1BANK       0x0032
  58 set IXP42x_SDRAM_32MB_4Mx16_2BANK       0x0033
  59 set IXP42x_SDRAM_32MB_8Mx16_1BANK       0x0010
  60 set IXP42x_SDRAM_64MB_8Mx16_2BANK       0x0011
  61 set IXP42x_SDRAM_64MB_16Mx16_1BANK      0x0012
  62 set IXP42x_SDRAM_128MB_16Mx16_2BANK     0x0013
  63 set IXP42x_SDRAM_128MB_32Mx16_1BANK     0x0014
  64 set IXP42x_SDRAM_256MB_32Mx16_2BANK     0x0015
  65
  66
  67 # helper function to init SDRAM on IXP42x.
  68 # SDRAM_CFG: one of IXP42X_SDRAM_xxx
  69 # REFRESH: refresh counter reload value (integer)
  70 # CASLAT: 2 or 3
  71 proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
  72
  73     switch $CASLAT {
  74         2 {
  75             set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ]
  76             set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
  77         }
  78         3 {
  79             set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ]
  80             set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
  81         }
  82         default { error [format "unsupported cas latency \"%s\" " $CASLAT] }
  83     }
  84     echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH]
  85
  86     mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3
  87     mww 0xCC000004          0 ;# disable refresh
  88     mww 0xCC000008          3 ;# NOP
  89     sleep 100
  90     mww 0xCC000004   $REFRESH ;# set refresh counter
  91     mww 0xCC000008          2 ;# Precharge All Banks
  92     sleep 100
  93     mww 0xCC000008          4 ;# Auto Refresh
  94     mww 0xCC000008          4 ;# Auto Refresh
  95     mww 0xCC000008          4 ;# Auto Refresh
  96     mww 0xCC000008          4 ;# Auto Refresh
  97     mww 0xCC000008          4 ;# Auto Refresh
  98     mww 0xCC000008          4 ;# Auto Refresh
  99     mww 0xCC000008          4 ;# Auto Refresh
 100     mww 0xCC000008          4 ;# Auto Refresh
 101     mww 0xCC000008    $CASCMD ;# Mode Select CL2/CL3
 102 }
 103
 104 proc ixp42x_set_bigendian { } {
 105     reg XSCALE_CTRL 0xF8
 106 }
 107