tcl/target/imx31.cfg

   1 # imx31 config
   2 #
   3
   4 reset_config trst_and_srst srst_gates_jtag
   5
   6 adapter_nsrst_delay 5
   7
   8 if { [info exists CHIPNAME] } {
   9    set _CHIPNAME $CHIPNAME
  10 } else {
  11    set _CHIPNAME imx31
  12 }
  13
  14 if { [info exists ENDIAN] } {
  15    set _ENDIAN $ENDIAN
  16 } else {
  17    set _ENDIAN little
  18 }
  19
  20 if { [info exists CPUTAPID] } {
  21    set _CPUTAPID $CPUTAPID
  22 } else {
  23    set _CPUTAPID 0x07b3601d
  24 }
  25
  26 if { [info exists SDMATAPID] } {
  27    set _SDMATAPID $SDMATAPID
  28 } else {
  29    set _SDMATAPID 0x2190101d
  30 }
  31
  32 if { [info exists ETBTAPID] } {
  33    set _ETBTAPID $ETBTAPID
  34 } else {
  35    set _ETBTAPID 0x2b900f0f
  36 }
  37
  38 #========================================
  39
  40 jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
  41
  42 # The "SDMA" - <S>mart <DMA> controller debug tap
  43 # Based on some IO pins - this can be disabled & removed
  44 # See diagram: 6-14
  45 #   SIGNAL NAME:
  46 #    SJC_MOD - controls multiplexer - disables ARM1136
  47 #    SDMA_BYPASS - disables SDMA    -
  48 #
  49 # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
  50 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
  51
  52 # No IDCODE for this TAP
  53 jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
  54
  55 # Per section 40.17.1, table 40-85 the IR register is 4 bits
  56 # But this conflicts with Diagram 6-13, "3bits ir and drs"
  57 jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
  58
  59 set _TARGETNAME $_CHIPNAME.cpu
  60 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
  61
  62
  63 proc power_restore {} { echo "Sensed power restore. No action." }
  64 proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
  65
  66 # trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
  67 etm config $_TARGETNAME 16 normal full etb
  68 etb config $_TARGETNAME $_CHIPNAME.etb