tcl/target/gp326xxxa.cfg

   1 #
   2 # Support for General Plus GP326XXXA chips
   3 #
   4
   5 if { [info exists CHIPNAME] } {
   6    set _CHIPNAME $CHIPNAME
   7 } else {
   8    set _CHIPNAME gp326xxxa
   9 }
  10
  11 if { [info exists ENDIAN] } {
  12    set _ENDIAN $ENDIAN
  13 } else {
  14    set _ENDIAN little
  15 }
  16
  17 if { [info exists CPUTAPID] } {
  18    set _CPUTAPID $CPUTAPID
  19 } else {
  20    set _CPUTAPID 0x4f1f0f0f
  21 }
  22
  23 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  24
  25 set _TARGETNAME $_CHIPNAME.cpu
  26
  27 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
  28
  29 # Use internal SRAM as a work area
  30 $_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0
  31
  32 # The chip has both lines connected together
  33 reset_config trst_and_srst srst_pulls_trst
  34 # This delay is needed otherwise communication with the target would
  35 # be unreliable
  36 adapter srst delay 100
  37
  38 # Set the adapter speed ridiculously low just in case we are
  39 # running off of a 32kHz clock
  40 adapter speed 2
  41
  42 proc gp32xxxa_halt_and_reset_control_registers {} {
  43         # System control registers
  44         set P_SYSTEM_CTRL_NEW       0xD0000008
  45         set P_SYSTEM_CTRL           0xD000000C
  46         set P_SYSTEM_CLK_EN0        0xD0000010
  47         set P_SYSTEM_CLK_EN1        0xD0000014
  48         set P_SYSTEM_RESET_FLAG     0xD0000018
  49         set P_SYSTEM_CLK_CTRL       0xD000001C
  50         set P_SYSTEM_LVR_CTRL       0xD0000020
  51         set P_SYSTEM_WATCHDOG_CTRL  0xD0000024
  52         set P_SYSTEM_PLLEN          0xD000005C
  53
  54         # Since we can't use SRST without pulling TRST
  55         # we can't assume the state of the clock configuration
  56         # or watchdog settings. So reset them before porceeding
  57
  58         # Set the adapter speed ridiculously low just in case we are
  59         # running off of a 32kHz clock
  60         adapter speed 2
  61
  62         # Disable any advanced features at this stage
  63         arm7_9 dcc_downloads disable
  64         arm7_9 fast_memory_access disable
  65
  66         # Do a "soft reset"
  67         soft_reset_halt
  68         # Reset all system control registers to their default "after-reset" values
  69         mwh $P_SYSTEM_WATCHDOG_CTRL  0x0000
  70         mwh $P_SYSTEM_LVR_CTRL       0x0000
  71
  72         mwh $P_SYSTEM_CTRL_NEW       0x0001
  73         mwh $P_SYSTEM_CTRL           0x0001
  74         # Clear all reset flags by writing 1's
  75         mwh $P_SYSTEM_RESET_FLAG     0x001C
  76
  77         mwh $P_SYSTEM_CLK_CTRL       0x8000
  78         mwh $P_SYSTEM_CLK_EN0        0xFFFF
  79         mwh $P_SYSTEM_CLK_EN1        0xFFFF
  80         mwh $P_SYSTEM_PLLEN          0x0010
  81
  82         # Unfortunately there's no register that would allow us to
  83         # know if PLL is locked. So just wait for 100ms in hopes that
  84         # it would be enough.
  85         sleep 100
  86
  87         # Now that we know that we are running at 48Mhz
  88         # Increase JTAG speed and enable speed optimization features
  89         adapter speed 5000
  90         arm7_9 dcc_downloads enable
  91         arm7_9 fast_memory_access enable
  92 }
  93
  94 $_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers }