tcl/target/davinci.cfg

   1 #
   2 # Utility code for DaVinci-family chips
   3 #
   4
   5 # davinci_pinmux:  assigns PINMUX$reg <== $value
   6 proc davinci_pinmux {soc reg value} {
   7         mww [expr [dict get $soc sysbase] + 4 * $reg] $value
   8 }
   9
  10 # mrw: "memory read word", returns value of $reg
  11 proc mrw {reg} {
  12         set value ""
  13         ocd_mem2array value 32 $reg 1
  14         return $value(0)
  15 }
  16
  17 # mmw: "memory modify word", updates value of $reg
  18 #       $reg <== ((value & ~$clearbits) | $setbits)
  19 proc mmw {reg setbits clearbits} {
  20         set old [mrw $reg]
  21         set new [expr ($old & ~$clearbits) | $setbits]
  22         mww $reg $new
  23 }
  24
  25 #
  26 # pll_setup: initialize PLL
  27 #  - pll_addr ... physical addr of controller
  28 #  - mult ... pll multiplier
  29 #  - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
  30 #
  31 # For PLLs that don't have a given register (e.g. plldiv8), or where a
  32 # given divider is non-programmable, caller provides *NO* config mapping.
  33 #
  34
  35 # PLL version 0x02: tested on dm355
  36 # REVISIT:  On dm6446/dm357 the PLLRST polarity is different.
  37 proc pll_v02_setup {pll_addr mult config} {
  38         set pll_ctrl_addr [expr $pll_addr + 0x100]
  39         set pll_ctrl [mrw $pll_ctrl_addr]
  40
  41         # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
  42         # NOTE:  this assumes we should clear that bit
  43         set pll_ctrl [expr $pll_ctrl & ~0x0100]
  44         mww $pll_ctrl_addr $pll_ctrl
  45
  46         # 2 - clear PLLENSRC (bit 5)
  47         set pll_ctrl [expr $pll_ctrl & ~0x0020]
  48         mww $pll_ctrl_addr $pll_ctrl
  49
  50         # 3 - clear PLLEN (bit 0) ... enter bypass mode
  51         set pll_ctrl [expr $pll_ctrl & ~0x0001]
  52         mww $pll_ctrl_addr $pll_ctrl
  53
  54         # 4 - wait at least 4 refclk cycles
  55         sleep 1
  56
  57         # 5 - set PLLRST (bit 3)
  58         set pll_ctrl [expr $pll_ctrl | 0x0008]
  59         mww $pll_ctrl_addr $pll_ctrl
  60
  61         # 6 - set PLLDIS (bit 4)
  62         set pll_ctrl [expr $pll_ctrl | 0x0010]
  63         mww $pll_ctrl_addr $pll_ctrl
  64
  65         # 7 - clear PLLPWRDN (bit 1)
  66         set pll_ctrl [expr $pll_ctrl & ~0x0002]
  67         mww $pll_ctrl_addr $pll_ctrl
  68
  69         # 8 - clear PLLDIS (bit 4)
  70         set pll_ctrl [expr $pll_ctrl & ~0x0010]
  71         mww $pll_ctrl_addr $pll_ctrl
  72
  73         # 9 - optional:  write prediv, postdiv, and pllm
  74         # NOTE:  for dm355 PLL1, postdiv is controlled via MISC register
  75         mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
  76         if { [dict exists $config prediv] } {
  77                 set div [dict get $config prediv]
  78                 set div [expr 0x8000 | ($div - 1)]
  79                 mww [expr $pll_addr + 0x0114] $div
  80         }
  81         if { [dict exists $config postdiv] } {
  82                 set div [dict get $config postdiv]
  83                 set div [expr 0x8000 | ($div - 1)]
  84                 mww [expr $pll_addr + 0x0128] $div
  85         }
  86
  87         # 10 - optional:  set plldiv1, plldiv2, ...
  88         # NOTE:  this assumes some registers have their just-reset values:
  89         #       - PLLSTAT.GOSTAT is clear when we enter
  90         #       - ALNCTL has everything set
  91         set go 0
  92         if { [dict exists $config div1] } {
  93                 set div [dict get $config div1]
  94                 set div [expr 0x8000 | ($div - 1)]
  95                 mww [expr $pll_addr + 0x0118] $div
  96                 set go 1
  97         }
  98         if { [dict exists $config div2] } {
  99                 set div [dict get $config div2]
 100                 set div [expr 0x8000 | ($div - 1)]
 101                 mww [expr $pll_addr + 0x011c] $div
 102                 set go 1
 103         }
 104         if { [dict exists $config div3] } {
 105                 set div [dict get $config div3]
 106                 set div [expr 0x8000 | ($div - 1)]
 107                 mww [expr $pll_addr + 0x0120] $div
 108                 set go 1
 109         }
 110         if { [dict exists $config div4] } {
 111                 set div [dict get $config div4]
 112                 set div [expr 0x8000 | ($div - 1)]
 113                 mww [expr $pll_addr + 0x0160] $div
 114                 set go 1
 115         }
 116         if { [dict exists $config div5] } {
 117                 set div [dict get $config div5]
 118                 set div [expr 0x8000 | ($div - 1)]
 119                 mww [expr $pll_addr + 0x0164] $div
 120                 set go 1
 121         }
 122         if {$go != 0} {
 123                 # write pllcmd.GO; poll pllstat.GO
 124                 mww [expr $pll_addr + 0x0138] 0x01
 125                 set pllstat [expr $pll_addr + 0x013c]
 126                 while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
 127         }
 128         mww [expr $pll_addr + 0x0138] 0x00
 129
 130         # 11 - wait at least 5 usec for reset to finish
 131         # (assume covered by overheads including JTAG messaging)
 132
 133         # 12 - clear PLLRST (bit 3)
 134         set pll_ctrl [expr $pll_ctrl & ~0x0008]
 135         mww $pll_ctrl_addr $pll_ctrl
 136
 137         # 13 - wait at least 8000 refclk cycles for PLL to lock
 138         # if we assume 24 MHz (slowest osc), that's 1/3 msec
 139         sleep 3
 140
 141         # 14 - set PLLEN (bit 0) ... leave bypass mode
 142         set pll_ctrl [expr $pll_ctrl | 0x0001]
 143         mww $pll_ctrl_addr $pll_ctrl
 144 }
 145
 146 # NOTE:  dm6446 requires EMURSTIE set in MDCTL before certain
 147 # modules can be enabled.
 148
 149 # prepare a non-DSP module to be enabled; finish with psc_go
 150 proc psc_enable {module} {
 151         set psc_addr 0x01c41000
 152         # write MDCTL
 153         mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
 154 }
 155
 156 # prepare a non-DSP module to be reset; finish with psc_go
 157 proc psc_reset {module} {
 158         set psc_addr 0x01c41000
 159         # write MDCTL
 160         mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
 161 }
 162
 163 # execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
 164 proc psc_go {} {
 165         set psc_addr 0x01c41000
 166         set ptstat_addr [expr $psc_addr + 0x0128]
 167
 168         # just in case PTSTAT.go isn't clear
 169         while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
 170
 171         # write PTCMD.go ... ignoring any DSP power domain
 172         mww [expr $psc_addr + 0x0120] 1
 173
 174         # wait for PTSTAT.go to clear (again ignoring DSP power domain)
 175         while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
 176 }
 177
 178 #
 179 # A reset using only SRST is a "Warm Reset", resetting everything in the
 180 # chip except ARM emulation (and everything _outside_ the chip that hooks
 181 # up to SRST).  But many boards don't expose SRST via their JTAG connectors
 182 # (it's not present on TI-14 headers).
 183 #
 184 # From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except
 185 # without any board-wide side effects, since it's triggered using JTAG using
 186 # either (a) ARM watchdog timer, or (b) ICEpick.
 187 #
 188 proc davinci_wdog_reset {} {
 189         set timer2_phys 0x01c21c00
 190
 191         # NOTE -- on entry
 192         #   - JTAG communication with the ARM *must* be working OK; this
 193         #     may imply using adaptive clocking or disabling WFI-in-idle
 194         #   - current target must be the DaVinci ARM
 195         #   - that ARM core must be halted
 196         #   - timer2 clock is still enabled (PSC 29 on most chips)
 197
 198         #
 199         # Part I -- run regardless of being halted via JTAG
 200         #
 201         # NOTE:  for now, we assume there's no DSP that could control the
 202         # watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog
 203         # suspend signal is controlled via ARM emulation suspend.
 204         #
 205
 206         # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
 207         mww phys [expr $timer2_phys + 0x28] 0x00004000
 208
 209         #
 210         # Part II -- in case watchdog hasn't been set up
 211         #
 212
 213         # TCR: disable, force internal clock source
 214         mww phys [expr $timer2_phys + 0x20] 0
 215
 216         # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
 217         mww phys [expr $timer2_phys + 0x24] 0
 218         mww phys [expr $timer2_phys + 0x24] 0x110b
 219
 220         # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
 221         # so watchdog triggers ASAP
 222         mww phys [expr $timer2_phys + 0x10] 0
 223         mww phys [expr $timer2_phys + 0x14] 0
 224         mww phys [expr $timer2_phys + 0x18] 0
 225         mww phys [expr $timer2_phys + 0x1c] 0
 226
 227         # WDTCR: put into pre-active state, then active
 228         mww phys [expr $timer2_phys + 0x28] 0xa5c64000
 229         mww phys [expr $timer2_phys + 0x28] 0xda7e4000
 230
 231         #
 232         # Part III -- it's ready to rumble
 233         #
 234
 235         # WDTCR: write invalid WDKEY to trigger reset
 236         mww phys [expr $timer2_phys + 0x28] 0x00004000
 237 }