tcl/target/davinci.cfg

   1 #
   2 # Utility code for DaVinci-family chips
   3 #
   4
   5 # davinci_pinmux:  assigns PINMUX$reg <== $value
   6 proc davinci_pinmux {soc reg value} {
   7         mww [expr [dict get $soc sysbase] + 4 * $reg] $value
   8 }
   9
  10 # mrw: "memory read word", returns value of $reg
  11 proc mrw {reg} {
  12         set value ""
  13         ocd_mem2array value 32 $reg 1
  14         return $value(0)
  15 }
  16
  17 # mmw: "memory modify word", updates value of $reg
  18 #       $reg <== ((value & ~$clearbits) | $setbits)
  19 proc mmw {reg setbits clearbits} {
  20         set old [mrw $reg]
  21         set new [expr ($old & ~$clearbits) | $setbits]
  22         mww $reg $new
  23 }
  24
  25 #
  26 # pll_setup: initialize PLL
  27 #  - pll_addr ... physical addr of controller
  28 #  - mult ... pll multiplier
  29 #  - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
  30 #
  31 # For PLLs that don't have a given register (e.g. plldiv8), or where a
  32 # given divider is non-programmable, caller provides *NO* config mapping.
  33 #
  34 # REVISIT there are minor differences between the PLL controllers.
  35 # Handle those; maybe check the ID register.  This version behaves
  36 # for at least the dm355.  On dm6446 and dm357 the PLLRST polarity
  37 # is different.  On dm365 there are more changes.
  38 #
  39 proc pll_setup {pll_addr mult config} {
  40         set pll_ctrl_addr [expr $pll_addr + 0x100]
  41         set pll_ctrl [mrw $pll_ctrl_addr]
  42
  43         # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
  44         # NOTE:  this assumes we should clear that bit
  45         set pll_ctrl [expr $pll_ctrl & ~0x0100]
  46         mww $pll_ctrl_addr $pll_ctrl
  47
  48         # 2 - clear PLLENSRC (bit 5)
  49         set pll_ctrl [expr $pll_ctrl & ~0x0020]
  50         mww $pll_ctrl_addr $pll_ctrl
  51
  52         # 3 - clear PLLEN (bit 0) ... enter bypass mode
  53         set pll_ctrl [expr $pll_ctrl & ~0x0001]
  54         mww $pll_ctrl_addr $pll_ctrl
  55
  56         # 4 - wait at least 4 refclk cycles
  57         sleep 1
  58
  59         # 5 - set PLLRST (bit 3)
  60         set pll_ctrl [expr $pll_ctrl | 0x0008]
  61         mww $pll_ctrl_addr $pll_ctrl
  62
  63         # 6 - set PLLDIS (bit 4)
  64         set pll_ctrl [expr $pll_ctrl | 0x0010]
  65         mww $pll_ctrl_addr $pll_ctrl
  66
  67         # 7 - clear PLLPWRDN (bit 1)
  68         set pll_ctrl [expr $pll_ctrl & ~0x0002]
  69         mww $pll_ctrl_addr $pll_ctrl
  70
  71         # 8 - clear PLLDIS (bit 4)
  72         set pll_ctrl [expr $pll_ctrl & ~0x0010]
  73         mww $pll_ctrl_addr $pll_ctrl
  74
  75         # 9 - optional:  write prediv, postdiv, and pllm
  76         # NOTE:  for dm355 PLL1, postdiv is controlled via MISC register
  77         mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
  78         if { [dict exists $config prediv] } {
  79                 set div [dict get $config prediv]
  80                 set div [expr 0x8000 | ($div - 1)]
  81                 mww [expr $pll_addr + 0x0114] $div
  82         }
  83         if { [dict exists $config postdiv] } {
  84                 set div [dict get $config postdiv]
  85                 set div [expr 0x8000 | ($div - 1)]
  86                 mww [expr $pll_addr + 0x0128] $div
  87         }
  88
  89         # 10 - optional:  set plldiv1, plldiv2, ...
  90         # NOTE:  this assumes some registers have their just-reset values:
  91         #       - PLLSTAT.GOSTAT is clear when we enter
  92         #       - ALNCTL has everything set
  93         set go 0
  94         if { [dict exists $config div1] } {
  95                 set div [dict get $config div1]
  96                 set div [expr 0x8000 | ($div - 1)]
  97                 mww [expr $pll_addr + 0x0118] $div
  98                 set go 1
  99         }
 100         if { [dict exists $config div2] } {
 101                 1et div [dict get $config div2]
 102                 set div [expr 0x8000 | ($div - 1)]
 103                 mww [expr $pll_addr + 0x011c] $div
 104                 set go 1
 105         }
 106         if { [dict exists $config div3] } {
 107                 set div [dict get $config div3]
 108                 set div [expr 0x8000 | ($div - 1)]
 109                 mww [expr $pll_addr + 0x011c] $div
 110                 set go 1
 111         }
 112         if { [dict exists $config div4] } {
 113                 set div [dict get $config div4]
 114                 set div [expr 0x8000 | ($div - 1)]
 115                 mww [expr $pll_addr + 0x0160] $div
 116                 set go 1
 117         }
 118         if { [dict exists $config div5] } {
 119                 set div [dict get $config div5]
 120                 set div [expr 0x8000 | ($div - 1)]
 121                 mww [expr $pll_addr + 0x0164] $div
 122                 set go 1
 123         }
 124         if {$go != 0} {
 125                 # write pllcmd.GO; poll pllstat.GO
 126                 mww [expr $pll_addr + 0x0138] 0x01
 127                 set pllstat [expr $pll_addr + 0x013c]
 128                 while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
 129         }
 130
 131         # 11 - wait at least 5 usec for reset to finish
 132         # (assume covered by overheads including JTAG messaging)
 133
 134         # 12 - clear PLLRST (bit 3)
 135         set pll_ctrl [expr $pll_ctrl & ~0x0008]
 136         mww $pll_ctrl_addr $pll_ctrl
 137
 138         # 13 - wait at least 8000 refclk cycles for PLL to lock
 139         # if we assume 24 MHz (slowest osc), that's 1/3 msec
 140         sleep 3
 141
 142         # 14 - set PLLEN (bit 0) ... leave bypass mode
 143         set pll_ctrl [expr $pll_ctrl | 0x0001]
 144         mww $pll_ctrl_addr $pll_ctrl
 145 }
 146
 147 # NOTE:  dm6446 requires EMURSTIE set in MDCTL before certain
 148 # modules can be enabled.
 149
 150 # prepare a non-DSP module to be enabled; finish with psc_go
 151 proc psc_enable {module} {
 152         set psc_addr 0x01c41000
 153         # write MDCTL
 154         mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
 155 }
 156
 157 # execute non-DSP PSC transition(s) set up by psc_enable
 158 proc psc_go {} {
 159         set psc_addr 0x01c41000
 160         set ptstat_addr [expr $psc_addr + 0x0128]
 161
 162         # just in case PTSTAT.go isn't clear
 163         while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
 164
 165         # write PTCMD.go ... ignoring any DSP power domain
 166         mww [expr $psc_addr + 0x0120] 1
 167
 168         # wait for PTSTAT.go to clear (again ignoring DSP power domain)
 169         while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
 170 }