tcl/target/c100config.tcl

   1
   2 # board(-config) specfic parameters file.
   3
   4 # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
   5 proc config {label} {
   6     return [dict get [configC100] $label ]
   7 }
   8
   9 # show the value for the param. with label
  10 proc showconfig {label} {
  11     puts [format "0x%x" [dict get [configC100] $label ]]
  12 }
  13
  14 # Telo board config
  15 # when there are more then one board config
  16 # use soft links to c100board-config.tcl
  17 # so that only the right board-config gets
  18 # included (just like include/configs/board-configs.h
  19 # in u-boot.
  20 proc configC100 {} {
  21     # xtal freq. 24MHz
  22     dict set configC100 CFG_REFCLKFREQ           24000000
  23
  24     # Amba Clk 165MHz
  25     dict set configC100 CONFIG_SYS_HZ_CLOCK      165000000
  26     dict set configC100 w_amba 1
  27     dict set configC100 x_amba 1
  28     # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
  29     dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
  30
  31     # Arm Clk 450MHz, must be a multiple of 25 MHz
  32     dict set configC100 CFG_ARM_CLOCK      450000000
  33     dict set configC100 w_arm 0
  34     dict set configC100 x_arm 1
  35     # y = arm_clk * (w+1)*(x+1)*2/xtal_clk
  36     dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
  37
  38
  39 }
  40
  41 proc setupNOR {} {
  42     puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
  43     # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
  44     set EX_CSEN_REG         [regs EX_CSEN_REG ]
  45     set EX_CS0_SEG_REG      [regs EX_CS0_SEG_REG ]
  46     set EX_CS0_CFG_REG      [regs EX_CS0_CFG_REG ]
  47     set EX_CS0_TMG1_REG     [regs EX_CS0_TMG1_REG ]
  48     set EX_CS0_TMG2_REG     [regs EX_CS0_TMG2_REG ]
  49     set EX_CS0_TMG3_REG     [regs EX_CS0_TMG3_REG ]
  50     set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
  51     set EX_MFSM_REG         [regs EX_MFSM_REG ]
  52     set EX_CSFSM_REG        [regs EX_CSFSM_REG ]
  53     set EX_WRFSM_REG        [regs EX_WRFSM_REG ]
  54     set EX_RDFSM_REG        [regs EX_RDFSM_REG ]
  55
  56     # enable Expansion Bus Clock + CS0 (NOR)
  57     mww $EX_CSEN_REG 0x3
  58     # set the address space for CS0=16MB
  59     mww $EX_CS0_SEG_REG 0x7ff
  60     # set the CS0 bus width to 16-bit
  61     mww $EX_CS0_CFG_REG 0x202
  62     # set timings to NOR
  63     mww $EX_CS0_TMG1_REG 0x03034006
  64     mww $EX_CS0_TMG2_REG 0x04040002
  65     #mww $EX_CS0_TMG3_REG
  66     # set EBUS clock 165/5=33MHz
  67     mww $EX_CLOCK_DIV_REG 0x5
  68     # everthing else is OK with default
  69 }
  70
  71 proc bootNOR {} {
  72     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
  73     set BLOCK_RESET_REG        [regs BLOCK_RESET_REG]
  74     set DDR_RST                [regs DDR_RST]
  75
  76     # put DDR controller in reset (so that it comes reset in u-boot)
  77     mmw $BLOCK_RESET_REG 0x0 $DDR_RST
  78     # setup CS0 controller for NOR
  79     setupNOR
  80     # make sure we are accessing the lower part of NOR
  81     lowGPIO5
  82     # set PC to start of NOR (at boot 0x20000000 = 0x0)
  83     reg pc $EXP_CS0_BASEADDR
  84     # run
  85     resume
  86 }
  87 proc setupGPIO {} {
  88     puts "Setting up GPIO block for Telo"
  89     # This is current setup for Telo (see sch. for details):
  90     #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
  91     #GPIO1 irq line for FXS-FXO
  92     #GPIO5 addr22 for NOR flash (access to upper 8MB)
  93     #GPIO17 reset for DECT module.
  94     #GPIO29 CS_n for NAND
  95
  96     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
  97     set GPIO_OE_REG                 [regs GPIO_OE_REG]
  98
  99     # set GPIO29=GPIO17=1, GPIO5=0
 100     mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
 101     # enable [as output] GPIO29,GPIO17,GPIO5
 102     mww $GPIO_OE_REG [expr  1<<29 | 1<<17 | 1<<5]
 103 }
 104
 105 proc highGPIO5 {} {
 106     puts "GPIO5 high"
 107     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
 108     # set GPIO5=1
 109     mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
 110 }
 111
 112 proc lowGPIO5 {} {
 113     puts "GPIO5 low"
 114     set GPIO_OUTPUT_REG             [regs GPIO_OUTPUT_REG]
 115     # set GPIO5=0
 116     mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
 117 }
 118
 119 proc boardID {id} {
 120     # so far built:
 121     # 4'b1111
 122     dict set boardID 15 name "EVT1"
 123     dict set boardID 15 ddr2size 128M
 124     # dict set boardID 15 nandsize 1G
 125     # dict set boardID 15 norsize 16M
 126     # 4'b0000
 127     dict set boardID 0 name "EVT2"
 128     dict set boardID 0 ddr2size 128M
 129     # 4'b0001
 130     dict set boardID 1 name "EVT3"
 131     dict set boardID 1 ddr2size 256M
 132     # 4'b1110
 133     dict set boardID 14 name "EVT3_old"
 134     dict set boardID 14 ddr2size 128M
 135     # 4'b0010
 136     dict set boardID 2 name "EVT4"
 137     dict set boardID 2 ddr2size 256M
 138
 139     return $boardID
 140 }
 141
 142 # converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
 143 # figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
 144 proc ooma_board_detect {} {
 145     set GPIO_BOOTSTRAP_REG      [regs GPIO_BOOTSTRAP_REG]
 146
 147     # read the current value of the BOOTSRAP pins
 148     set tmp [mrw $GPIO_BOOTSTRAP_REG]
 149     puts [format "GPIO_BOOTSTRAP_REG  (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
 150     # extract the GPBP bits
 151     set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3]
 152
 153     # display board ID
 154     puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
 155     # return the ddr2 size, used to configure DDR2 on a given board.
 156     return [dict get [boardID $gpbt] $gpbt ddr2size]
 157 }
 158
 159 proc configureDDR2regs_256M {} {
 160     puts "ConfigureDDR2regs_256M TBD"
 161 }
 162
 163 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
 164 # The values are computed based on Mindspeed and Nanya datasheets
 165 proc configureDDR2regs_128M {} {
 166
 167     set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
 168     set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
 169     set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
 170     set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
 171     set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
 172     set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
 173     set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
 174     set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
 175     set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
 176     set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
 177     set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
 178     set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
 179     set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
 180     set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
 181     set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
 182     set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
 183     set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
 184     set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
 185     set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
 186     set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
 187     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
 188
 189
 190     set DENALI_CTL_02_VAL 0x0100010000010100
 191     set DENALI_CTL_11_VAL 0x433A42124A650A37
 192     # set some default values
 193     mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
 194     mw64bit $DENALI_CTL_01_DATA  0x0100000100000101
 195     mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
 196     mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
 197     mw64bit $DENALI_CTL_04_DATA  0x0201010100000201
 198     mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
 199     mw64bit $DENALI_CTL_06_DATA  0x050A020200020202
 200     mw64bit $DENALI_CTL_07_DATA  0x000000030E0B0205
 201     mw64bit $DENALI_CTL_08_DATA  0x6427003F3F0A0209
 202     mw64bit $DENALI_CTL_09_DATA  0x1A00002F00001A00
 203     mw64bit $DENALI_CTL_10_DATA  0x01202020201A1A1A
 204     mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
 205     mw64bit $DENALI_CTL_12_DATA  0x0000080000000800
 206     mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
 207     mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
 208     mw64bit $DENALI_CTL_15_DATA  0x0508000000000000
 209     mw64bit $DENALI_CTL_16_DATA  0x000020472D200000
 210     mw64bit $DENALI_CTL_17_DATA  0x0000000008000000
 211     mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
 212     mw64bit $DENALI_CTL_19_DATA  0x00001400C8030604
 213     mw64bit $DENALI_CTL_20_DATA  0x00000000823600C8
 214
 215     set wr_dqs_shift 0x40
 216     # start DDRC
 217     mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
 218     # wait int_status[2] (DRAM init complete)
 219     puts -nonewline "Waiting for DDR2 controller to init..."
 220     set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
 221     while { [expr $tmp & 0x040000] == 0 } {
 222         sleep 1
 223         set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
 224     }
 225    mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL  & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
 226     puts "done."
 227
 228     # do ddr2 training sequence
 229     # TBD (for now, if you need it, run trainDDR command)
 230 }
 231
 232
 233
 234 proc setupUART0 {} {
 235     # configure UART0 to 115200, 8N1
 236     set GPIO_LOCK_REG      [regs GPIO_LOCK_REG]
 237     set GPIO_IOCTRL_REG    [regs GPIO_IOCTRL_REG]
 238     set GPIO_IOCTRL_VAL    [regs GPIO_IOCTRL_VAL]
 239     set GPIO_IOCTRL_UART0  [regs GPIO_IOCTRL_UART0]
 240     set UART0_LCR                   [regs UART0_LCR]
 241     set LCR_DLAB                    [regs LCR_DLAB]
 242     set UART0_DLL                   [regs UART0_DLL]
 243     set UART0_DLH                   [regs UART0_DLH]
 244     set UART0_IIR                   [regs UART0_IIR]
 245     set UART0_IER                   [regs UART0_IER]
 246     set LCR_ONE_STOP                [regs LCR_ONE_STOP]
 247     set LCR_CHAR_LEN_8              [regs LCR_CHAR_LEN_8]
 248     set FCR_XMITRES                 [regs FCR_XMITRES]
 249     set FCR_RCVRRES                 [regs FCR_RCVRRES]
 250     set FCR_FIFOEN                  [regs FCR_FIFOEN]
 251     set IER_UUE                     [regs IER_UUE]
 252
 253     # unlock writing to IOCTRL register
 254     mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
 255     # enable UART0
 256     mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
 257     # baudrate  115200
 258     # This should really be amba_clk/(16*115200) but amba_clk=165MHz
 259     set tmp 89
 260     # Enable Divisor Latch access
 261     mmw  $UART0_LCR $LCR_DLAB 0x0
 262     # set the divisor to $tmp
 263     mww $UART0_DLL [expr $tmp & 0xff]
 264     mww $UART0_DLH [expr $tmp >> 8]
 265     # Disable Divisor Latch access
 266     mmw  $UART0_LCR 0x0 $LCR_DLAB
 267     # set the UART to 8N1
 268     mmw  $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0
 269     # reset FIFO
 270     mmw  $UART0_IIR [expr $FCR_XMITRES  | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0
 271     #  enable FFUART
 272     mww $UART0_IER $IER_UUE
 273 }
 274
 275 proc putcUART0 {char} {
 276
 277     set UART0_LSR           [regs UART0_LSR]
 278     set UART0_THR           [regs UART0_THR]
 279     set LSR_TEMT            [regs LSR_TEMT]
 280
 281     # convert the 'char' to digit
 282     set tmp [ scan $char %c ]
 283     # /* wait for room in the tx FIFO on FFUART */
 284     while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 }
 285     mww $UART0_THR $tmp
 286     if { $char == "\n" } { putcUART0 \r }
 287 }
 288
 289 proc putsUART0 {str} {
 290     set index 0
 291     set len [string length $str]
 292     while { $index < $len } {
 293         putcUART0 [string index $str $index]
 294         set index [expr $index + 1]
 295     }
 296 }
 297
 298
 299 proc trainDDR2 {} {
 300     set ARAM_BASEADDR   [regs ARAM_BASEADDR]
 301
 302     # you must have run 'reset init' or u-boot
 303     # load the training code to ARAM
 304     load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
 305     # set PC to start of NOR (at boot 0x20000000 = 0x0)
 306     reg pc $ARAM_BASEADDR
 307     # run
 308     resume
 309 }
 310
 311 proc flashUBOOT {} {
 312     # this will update uboot on NOR partition
 313     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
 314
 315     # setup CS0 controller for NOR
 316     setupNOR
 317     # make sure we are accessing the lower part of NOR
 318     lowGPIO5
 319     flash probe 0
 320     puts "Erasing sectors 0-3 for uboot"
 321     flash erase_sector 0 0 3
 322     puts "Programming u-boot, takes about 4-5 min for 256kb"
 323     flash write_image ./images/u-boot.bin $EXP_CS0_BASEADDR
 324 }