tcl/target/atheros_ar9331.cfg

   1 if { [info exists CHIPNAME] } {
   2         set _CHIPNAME $_CHIPNAME
   3 } else {
   4         set _CHIPNAME ar9331
   5 }
   6
   7 if { [info exists CPUTAPID] } {
   8         set _CPUTAPID $CPUTAPID
   9 } else {
  10         set _CPUTAPID 0x00000001
  11 }
  12
  13 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
  14
  15 set _TARGETNAME $_CHIPNAME.cpu
  16 target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
  17
  18 proc ar9331_25mhz_pll_init {} {
  19         mww 0xb8050008 0x00018004       ;# bypass PLL; AHB_POST_DIV - ratio 4
  20         mww 0xb8050004 0x00000352       ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
  21         mww 0xb8050000 0x40818000       ;# Power down control for CPU PLL
  22                                         ;# OUTDIV | REFDIV | DIV_INT
  23         mww 0xb8050010 0x001003e8       ;# CPU PLL Dither FRAC Register
  24                                         ;# (disabled?)
  25         mww 0xb8050000 0x00818000       ;# Power on | OUTDIV | REFDIV | DIV_INT
  26         mww 0xb8050008 0x00008000       ;# remove bypass;
  27                                         ;# AHB_POST_DIV - ratio 2
  28 }
  29
  30 proc ar9331_ddr1_init {} {
  31         mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
  32         mww 0xb8000004 0x9dd0e6a8       ;# DDR_CONFIG2 - more DRAM confs
  33
  34         mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
  35         mww 0xb8000008 0x133    ;# mode reg: 0x133 - default
  36         mww 0xb8000010 0x1      ;# Forces an MRS update cycl
  37         mww 0xb800000c 0x2      ;# Extended mode register value.
  38                                 ;# default 0x2 - Reset to weak driver, DLL on
  39         mww 0xb8000010 0x2      ;# Forces an EMRS update cycle
  40         mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
  41         mww 0xb8000008 0x33     ;# mode reg: remove some bit?
  42         mww 0xb8000010 0x1      ;# Forces an MRS update cycl
  43         mww 0xb8000014 0x4186   ;# enable refres: bit(14) - set refresh rate
  44         mww 0xb800001c 0x8      ;# This register is used along with DQ Lane 0,
  45                                 ;# DQ[7:0], DQS_0
  46         mww 0xb8000020 0x9      ;# This register is used along with DQ Lane 1,
  47                                 ;# DQ[15:8], DQS_1.
  48         mww 0xb8000018 0xff     ;# DDR read and capture bit mask.
  49                                 ;# Each bit represents a cycle of valid data.
  50 }
  51
  52 proc ar9331_ddr2_init {} {
  53         mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
  54         mww 0xb8000004 0x9dd0e6a8       ;# DDR_CONFIG2 - more DRAM confs
  55
  56         mww 0xb800008c 0x00000a59
  57         mww 0xb8000010 0x00000008       ;# PRECHARGE ALL cycle
  58
  59         mww 0xb8000090 0x00000000
  60         mww 0xb8000010 0x00000010       ;# EMR2S update cycle
  61
  62         mww 0xb8000094 0x00000000
  63         mww 0xb8000010 0x00000020       ;# EMR3S update cycle
  64
  65         mww 0xb800000c 0x00000000
  66         mww 0xb8000010 0x00000002       ;# EMRS update cycle
  67
  68         mww 0xb8000008 0x00000100
  69         mww 0xb8000010 0x00000001       ;# MRS update cycle
  70
  71         mww 0xb8000010 0x00000008       ;# PRECHARGE ALL cycle
  72
  73         mww 0xb8000010 0x00000004
  74         mww 0xb8000010 0x00000004       ;# AUTO REFRESH cycle
  75
  76         mww 0xb8000008 0x00000a33
  77         mww 0xb8000010 0x00000001       ;# MRS update cycle
  78
  79         mww 0xb800000c 0x00000382
  80         mww 0xb8000010 0x00000002       ;# EMRS update cycle
  81
  82         mww 0xb800000c 0x00000402
  83         mww 0xb8000010 0x00000002       ;# EMRS update cycle
  84
  85         mww 0xb8000014 0x00004186       ;# DDR_REFRESH
  86         mww 0xb800001c 0x00000008       ;# DDR_TAP_CTRL0
  87         mww 0xb8000020 0x00000009       ;# DDR_TAP_CTRL1
  88
  89         ;# DDR read and capture bit mask.
  90         ;# Each bit represents a cycle of valid data.
  91         ;# 0xff: use 16-bit DDR
  92         mww 0xb8000018 0x000000ff
  93 }